Data-Width-Driven Power Gating of Integer Arithmetic Circuits
Paper in proceeding, 2012

When performing narrow-width computations, power gating of unused arithmetic circuit portions can significantly reduce leakage power. We deploy coarse-grain power gating in 32-bit integer arithmetic circuits that frequently will operate on narrow-width data. Our contributions include a design framework that automatically implements coarse-grain power-gated arithmetic circuits considering a narrow-width input data mode, and an analysis of the impact of circuit architecture on the efficiency of this data-width-driven power gating scheme. As an example, with a performance penalty of 6.7%, coarse-grain power gating of a 45-nm 32-bit multiplier is demonstrated to yield an 11.6x static leakage energy reduction per 8x8-bit operation.


Tung Hoang

Chalmers, Computer Science and Engineering (Chalmers), Computer Engineering (Chalmers)

Per Larsson-Edefors

Chalmers, Computer Science and Engineering (Chalmers), Computer Engineering (Chalmers)

Proceedings of IEEE Computer Society Annual Symposium on VLSI (ISVLSI), Amherst, 19-21 August 2012

Article number 6296479 237-242 6296479
978-076954767-1 (ISBN)

Areas of Advance

Information and Communication Technology


Driving Forces

Sustainable development

Subject Categories

Other Electrical Engineering, Electronic Engineering, Information Engineering





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