Speculative Tag Access for Reduced Energy Dissipation in Set-Associative L1 Data Caches
Paper in proceedings, 2013

Due to performance reasons, all ways in set-associative level-one (L1) data caches are accessed in parallel for load operations even though the requested data can only reside in one of the ways. Thus, a significant amount of energy is wasted when loads are performed. We propose a speculation technique that performs the tag comparison in parallel with the address calculation, leading to the access of only one way during the following cycle on successful speculations. The technique incurs no execution time penalty, has an insignificant area overhead, and does not require any customized SRAM implementation. Assuming a 16kB 4-way set-associative L1 data cache implemented in a 65-nm process technology, our evaluation based on 20 different MiBench benchmarks shows that the proposed technique on average leads to a 24% data cache energy reduction.

Author

Alen Bardizbanyan

Chalmers, Computer Science and Engineering (Chalmers), Computer Engineering (Chalmers)

Magnus Själander

Chalmers, Computer Science and Engineering (Chalmers), Computer Engineering (Chalmers)

David Whalley

Per Larsson-Edefors

Chalmers, Computer Science and Engineering (Chalmers), Computer Engineering (Chalmers)

Proceedings of IEEE International Conference on Computer Design (ICCD), Asheville, NC, USA, October 6-9 2013

302-308

Areas of Advance

Information and Communication Technology

Energy

Driving Forces

Sustainable development

Subject Categories

Computer Systems

More information

Created

10/7/2017