3D chip stacking using planarized carbon nanotubes as through-silicon-vias
Conference contribution, 2009
Author
Kjell Jeppson
Chalmers, Applied Physics, Physical Electronics
Teng Wang
Chalmers, Applied Physics, Electronics Material and Systems Laboratory
Johan Liu
Chalmers, Applied Physics, Electronics Material and Systems Laboratory
Per Larsson-Edefors
Chalmers, Computer Science and Engineering (Chalmers), Computer Engineering (Chalmers)
Swedish System on Chip Conference
Subject Categories
Electrical Engineering, Electronic Engineering, Information Engineering