Kjell Jeppson
Showing 128 publications
VLSI kretskonstruktion och avancerad mikroelektronik 1972-1988
A Parameter Extraction Methodology for Graphene Field-Effect-Transistors
A two-step parameter extraction methodology for graphene field-effect transistors
Graphene FET on diamond for high-frequency electronics
Mobility degradation and series resistance in graphene field-effect transistors
A linear-array of 300-GHz antenna integrated GFET detectors on a flexible substrate
Describing broadband terahertz response of graphene FET detectors by a classical model
Properties of Undoped Few-Layer Graphene-Based Transparent Heaters
Wide Bandwidth Terahertz Mixers Based On Graphene FETs
Thermal Characterization of Low-Dimensional Materials by Resistance Thermometers
Low-frequency Noise Characterization of Graphene FET THz Detectors
Improving Thermal Transport at Carbon Hybrid Interfaces by Covalent Bonds
Test structures for studying flexible interconnect supported by carbon nanotube scaffolds
A flexible and stackable 3D interconnect system using growth-engineered carbon nanotube scaffolds
Chemical vapor deposition grown graphene on Cu-Pt alloys
2D HEAT DISSIPATION MATERIALS FOR MICROELECTRONICS COOLING APPLICATIONS
The Effects of Graphene-Based Films as Heat Spreaders for Thermal Management in Electronic Packaging
Vertically aligned CNT-Cu nano-composite material for stacked through-silicon-via interconnects
Embedded Fin-Like Metal/CNT Hybrid Structures for Flexible and Transparent Conductors
Enhanced Cold Wall CVD Reactor Growth of Horizontally Aligned Single-walled Carbon Nanotubes
Synthesis and Applications of Two-Dimensional Hexagonal Boron Nitride in Electronics Manufacturing
Finite element simulation of 2D-based materials as heat spreaders
Large area and uniform monolayer graphene CVD growth on oxidized copper in a cold wall reactor
Improved Heat Spreading Performance of Functionalized Graphene in Microelectronic Device Application
Vertically stacked carbon nanotube-based interconnects for through silicon via application
Tape-Assisted Transfer of Carbon Nanotube Bundles for Through-Silicon-Via Applications
Cooling Hot Spots by hexagonal Boron Nitride Heat Spreaders
Timing- and power-driven ALU design training using spreadsheet-based arithmetic exploration
Three- and Four-Point Hamer-type MOSFET Parameter Extraction Methods Revisited
Exploring prefix-tree adders using excel spreadsheets
A learning tool MOSFET model A stepping-stone from the square-law model to BSIM4
Training Design Methodology Skills at the Master’s Level
Through-Silicon Vias Filled With Densified and Transferred Carbon Nanotube Forests
Formation of three-dimensional carbon nanotube structures by controllable vapor densification
Electrical Interconnects Made of Carbon Nanotubes: Applications in 3D Chip Stacking
Carbon Nanotubes in Electronics Interconnect Applications with a Focus on 3D-TSV Technology
Benchmarking assembly materials for vertically aligned carbon nanotubes into microsystems
Carbon-Nanotube Through-Silicon Via Interconnects for Three-Dimensional Integration
Dry densification of carbon nanotube bundles
3D chip stacking using planarized carbon nanotubes as through-silicon-vias
Through silicon vias filled with planarized carbon nanotube bundles
Increasing student examination rate by use of weekly home assignments
Microelectronics based on Linear Relationships
Noise Interaction Between Power Distribution Grids and Substrate
A New Master's Program in Integrated Electronic System Design
Evaluation of Active Cancellation of Substrate-Noise in Mixed-Signal ICs
Exposed Datapath for Efficient Computing
Evaluation of Using Active Circuitry for Substrate Noise Suppression
Compact Spreading Resistance Model for Rectangular Contacts on Uniform and Epitaxial Substrates
Properties and Modeling of Ground Structures for Reducing Substrate Noise Coupling in ICs
MOSFET Modelling for the new millenium
Exposed Datapath for Efficient Computing
gm/ID-related MOSFET modeling for analog circuit design
Substrate Noise Reduction Using Active Circuitry
A High-Frequency Extension of a Surface-Potential-Based Substrate Model for Noise Coupling Analysis
gm/IDS-related MOSFET Modelling for Analog Circuit Design
Lab on the Web - Looking at Different Ways of Experiencing Electronic Experiments
Piece-wise modelling - bringing the essentials of MOSFET modelling to a new student generation
MOSFET Modelling for Non-Physics Undergraduate Students in the First Decade of the New Millenium
Modeling of Rectangular Contacts for Noise Coupling Analysis in Homogeneous Substrates
A Surface Potential Model for Predicting Substrate Noise Coupling in Integrated Circuits
Influence of Guard Bands on Substrate Noise Coupling
A Surface Potential Model for Predicting Substrate Noise Coupling in Integrated Circuits
Resistance Modeling in 1D, 2D, and 3D for Substrate Networks
SHARING ONLINE LABORATORIES AND THEIR COMPONENTS - A new learning experience
Theory of a room-temperature silicon quantum dot device as a sensitive electrometer
FlexSoC: Combining Flexibility and Efficiency in SoC Designs
Resistance Modelling in 1D, 2D, and 3D for Substrate Networks
An Accurate Pi Resistor Network for Substrate Coupling Estimation
Substrate Resistance Modelling in One, Two and Three Dimensions
Substrate Resistance Modeling for Noise Coupling Analysis
A new test structure for parasitic resistance extraction in bipolar transistors
Extraction of the intrinsic base region sheet resistance in bipolar transistors
On DC modeling of the base resistance in bipolar transistors
Stress and recovery transients in bipolar transistors and MOS structures
A new procedure for extraction of series resistances for bipolar transistors from DC measurements
Parameter extraction for bipolar transistors
Static Characterization and parameter Extraction in MOS Transistors
A new direct extraction algorithm for intrinsic Gummel-Poon BJT model parameters
Test chip and data considerations for MOS parameter extraction
A new method of determining the effective channel width and its dependence on the gate voltage
Direct extraction of MOS transistor model parameters
Analytical extraction method for submicron MOS transistor model parameters in the linear region
A direct method to extract effective geometries and series resistances of MOS transistors
Single Event Upset Behavior of CMOS Static RAM Cells
Comments on "A module generator for optimized CMOS buffers"
A direct extraction algorithm for a submicron MOS transistor model
Formal definitions of edge-based geometric design rules
The halo algorithm-an algorithm for hierarchical design of rule checking of VLSI circuits
Extraction of series-resistance-independent MOS transistor model parameters
A parallel hierarchical design rule checker
An efficient parameter extraction algorithm for MOS transistor models
A fast method of parameter extraction for MOS transistors
The Use of Inverse Layout Trees for Hierarchical Design Rule Checking
Dynamic Rams - how they developed during the late 1970´s
The Use of Inverse Layout Trees for Hierarchical Design Rule Checking
New algorithms for increased efficiency in hierarchical design rule checking
CMOS Circuit Speed and Buffer Optimization
A Physical Approach of MNOS LSI Memory Testing
Retention Testing of MNOS LSI Memories
Negative bias stress of MOS devices at high electric fields and degradation of MNOS devices
Unintentional writing of a FAMOS memory device during reading
Influence of the channel width on the threshold voltage modulation in MOSFETs
A content-addressable memory cell with MNOS transistors
Download publication list
You can download this list to your computer.
Filter and download publication list
As logged in user (Chalmers employee) you find more export functions in MyResearch.
You may also import these directly to Zotero or Mendeley by using a browser plugin. These are found herer:
Zotero Connector
Mendeley Web Importer
The service SwePub offers export of contents from Research in other formats, such as Harvard and Oxford in .RIS, BibTex and RefWorks format.
Showing 1 research projects
Thermal management with carbon nanotube architectures (THEMA-CNT)