Kjell Jeppson

Professor at Chalmers, Computer Science and Engineering (Chalmers), Computer Engineering (Chalmers), Electronics Systems

Involved in research concerning aspects of application specific integrated circuit (ASIC) design, 3D integration and signal integrity, growth of carbon nanotubes for through-silicon-vias, transistor modelling and parameter extraction.Technical Program Committee Member of the following conferencesNorchip - the annual Nordic ASIC EventICMTS - the International Conference on Microelectronic Test StructuresEWME - The European Workshop on Microelectronics Education

Source: chalmers.se

Showing 113 publications

2019

Wide Bandwidth Terahertz Mixers Based On Graphene FETs

Xinxin Yang, Andrei Vorobiev, Kjell Jeppson et al
Paper in proceedings
2018

Low-frequency Noise Characterization of Graphene FET THz Detectors

Xinxin Yang, Andrei Vorobiev, Kjell Jeppson et al
Paper in proceedings
2018

Improving Thermal Transport at Carbon Hybrid Interfaces by Covalent Bonds

Majid Kabiri Samani, Shuangxi Sun, Yifeng Fu et al
Advanced Materials Interfaces. Vol. 2018 (5)
Journal article
2018

Test structures for evaluating Al2O3 dielectrics for graphene field effect transistors on flexible substrates

Xinxin Yang, Marlene Bonmann, Andrei Vorobiev et al
Proceedings of the 2018 IEEE International Conference on Microelectronic Test Structures. Vol. 31, p. 75-78
Paper in proceedings
2017

Test structures for studying flexible interconnect supported by carbon nanotube scaffolds

Kjell Jeppson, Di Jiang, Shuangxi Sun et al
International Conference on Microelectronic Test Structures. Vol. 2017
Paper in proceedings
2017

A flexible and stackable 3D interconnect system using growth-engineered carbon nanotube scaffolds

Di Jiang, Shuangxi Sun, Michael Edwards et al
Flexible and Printed Electronics. Vol. 2 (2)
Journal article
2017

Chemical vapor deposition grown graphene on Cu-Pt alloys

Yong Zhang, Yifeng Fu, Michael Edwards et al
Materials Letters. Vol. 193, p. 255-258
Journal article
2016

2D HEAT DISSIPATION MATERIALS FOR MICROELECTRONICS COOLING APPLICATIONS

Yong Zhang, S. Huang, Nan Wang et al
China Semiconductor Technology International Conference (CSTIC) (Shanghai, March 13-14)
Conference contribution
2016

Controllable and fast synthesis of bilayer graphene by chemical vapor deposition on copper foil using a cold wall reactor

Wei Mu, Yifeng Fu, Shuangxi Sun et al
Chemical Engineering Journal. Vol. 304 (15 November 2016), p. 106-114
Journal article
2016

The Effects of Graphene-Based Films as Heat Spreaders for Thermal Management in Electronic Packaging

Shirong Huang, Jie Bao, N. Wang et al
2016 17th International Conference on Electronic Packaging Technology, ICEPT 2016, p. Art no 7583272; Pages 889-892
Paper in proceedings
2016

Vertically aligned CNT-Cu nano-composite material for stacked through-silicon-via interconnects

Shuangxi Sun, Wei Mu, Michael Edwards et al
Nanotechnology. Vol. 27 (33), p. Art no335705-
Journal article
2016

Embedded Fin-Like Metal/CNT Hybrid Structures for Flexible and Transparent Conductors

Di Jiang, Nan Wang, Michael Edwards et al
Small. Vol. 12 (11), p. 1521-1526
Journal article
2016

Hotspot test structures for evaluating carbon nanotube microfin coolers and graphene-like heat spreaders

Kjell Jeppson, Jie Bao, S. Huang et al
29th IEEE International Conference on Microelectronic Test Structures (ICMTS), Yokohama, Japan, Mar 28-31, 2016, p. 32-36
Paper in proceedings
2016

Characterization and simulation of liquid phase exfoliated graphene-based films for heat spreading applications

Yong Zhang, Michael Edwards, Kabir Majid Samani et al
Carbon. Vol. 106, p. 195-201
Journal article
2016

Enhanced Cold Wall CVD Reactor Growth of Horizontally Aligned Single-walled Carbon Nanotubes

Wei Mu, Eun-Hye Kwak, Bingan Chen et al
Electronic Materials Letters. Vol. 12 (3), p. 329-337
Journal article
2016

Double-Densified VerticallyAligned Carbon Nanotube Bundles for Application in 3D Integration High Aspect Ratio TSV Interconnects

Wei Mu, Josef Hansson, Shuangxi Sun et al
66th IEEE Electronic Components and Technology Conference (ECTC), Las Vegas, USA, May 31-Jun 03, 2016, p. 211-216
Paper in proceedings
2016

Infrared Emissivity Measurement for Vertically Aligned Multiwall Carbon Nanotubes (CNTs) Based Heat Spreader Applied in High Power Electronics Packaging

Shirong Huang, N. Wang, Jie Bao et al
6th Electronic System-integration Technology Conference (ESTC 2016), p. Article no 7764696-
Paper in proceedings
2016

Two-dimensional hexagonal boron nitride as lateral heat spreader in electrically insulating packaging

Jie Bao, Michael Edwards, Shirong Huang et al
Journal of Physics D: Applied Physics. Vol. 49 (July 2016), p. 265501-
Journal article
2016

Synthesis and Applications of Two-Dimensional Hexagonal Boron Nitride in Electronics Manufacturing

Jie Bao, Kjell Jeppson, Michael Edwards et al
Electronic Materials Letters. Vol. 12 (1), p. 1-16
Journal article
2016

Finite element simulation of 2D-based materials as heat spreaders

Michael Edwards, Yong Zhang, Jie Bao et al
IMAPS Nordic Annual Conference 2016 Proceedings
Paper in proceedings
2016

Large area and uniform monolayer graphene CVD growth on oxidized copper in a cold wall reactor

Wei Mu, Yifeng Fu, Shuangxi Sun et al
IMAPS Nordic Annual Conference 2016 Proceedings
Paper in proceedings
2015

Improved Heat Spreading Performance of Functionalized Graphene in Microelectronic Device Application

Yong Zhang, H. X. Han, Nan Wang et al
Advanced Functional Materials. Vol. 25 (28), p. 4430-4435
Journal article
2015

Vertically stacked carbon nanotube-based interconnects for through silicon via application

Di Jiang, Wei Mu, Si Chen et al
IEEE Electron Device Letters. Vol. 36 (5), p. 499-501
Journal article
2015

Tape-Assisted Transfer of Carbon Nanotube Bundles for Through-Silicon-Via Applications

Wei Mu, Shuangxi Sun, Di Jiang et al
Journal of Electronic Materials. Vol. 2015 (17 April), p. http://dx.doi.org/10.1007/s11664-015-3752-2-
Journal article
2015

Cooling Hot Spots by hexagonal Boron Nitride Heat Spreaders

Kjell Jeppson
Invited talk, International Graphene Innovation Conference (GrapChina), Qingdao
Conference contribution
2014

Timing- and power-driven ALU design training using spreadsheet-based arithmetic exploration

Per Larsson-Edefors, Kjell Jeppson
10th European Workshop on Microelectronics Education, EWME 2014, p. 151-154
Paper in proceedings
2013

Three- and Four-Point Hamer-type MOSFET Parameter Extraction Methods Revisited

Kjell Jeppson
IEEE International Conference on Microelectronic Test Structures (ICMTS 2013) (Osaka, Japan), p. 141-145
Paper in proceedings
2013

Exploring prefix-tree adders using excel spreadsheets

Kjell Jeppson, Per Larsson-Edefors
2013 9th IEEE International Conference on Microelectronic Systems Education, MSE 2013. Vol. Austin, Texas 2-3 June 2013, p. 48-51
Paper in proceedings
2013

A learning tool MOSFET model A stepping-stone from the square-law model to BSIM4

Kjell Jeppson
23rd International Workshop on Power And Timing Modeling, Optimization and Simulation, PATMOS 2013. Karlsruhe, Deutschland. SEP 09-11, 2013, p. 39-44
Paper in proceedings
2012

Training Design Methodology Skills at the Master’s Level

Per Larsson-Edefors, Kjell Jeppson
European Workshop on Microelectronics Education. Vol. 2012 (9-11 May, 2012), p. 10-13
Paper in proceedings
2012

Through-Silicon Vias Filled With Densified and Transferred Carbon Nanotube Forests

Kjell Jeppson, Teng Wang, Di Jiang et al
IEEE Electron Device Letters. Vol. 33 (3), p. 420-422
Journal article
2012

Formation of three-dimensional carbon nanotube structures by controllable vapor densification

Teng Wang, Di Jiang, Si Chen et al
Materials Letters. Vol. 78, p. 184-187
Journal article
2012

Electrical Interconnects Made of Carbon Nanotubes: Applications in 3D Chip Stacking

Di Jiang, Lilei Ye, Kjell Jeppson et al
IMAPS Nordic Annual Conference Proceedings 2012, Helsingor, 2 - 4 September 2012, p. 150-159
Paper in proceedings
2012

Carbon Nanotubes in Electronics Interconnect Applications with a Focus on 3D-TSV Technology

Di Jiang, Teng Wang, Lilei Ye et al
ECS Transactions. Vol. 44 (1), p. 683-692
Paper in proceedings
2011

Benchmarking assembly materials for vertically aligned carbon nanotubes into microsystems

Teng Wang, Nabi Nabiollahi, Kjell Jeppson et al
CD Proceedings of the Annual World Conference on Carbon, ECUST, Shanghai, China, July 25-29, 2011, Paper no: 740
Paper in proceedings
2011

Carbon-Nanotube Through-Silicon Via Interconnects for Three-Dimensional Integration

Teng Wang, Kjell Jeppson, L. Ye et al
Small. Vol. 7 (16), p. 2313-2317
Journal article
2010

Implementing Constructive Alignment in a CDIO-oriented Master’s Program in Integrated Electronic System Design

Kjell Jeppson, Lena Peterson, Lars Svensson et al
Proceedings of European Workshop on Microelectronics Education, p. 135-140
Paper in proceedings
2010

Dry densification of carbon nanotube bundles

Teng Wang, Kjell Jeppson, Johan Liu
Carbon. Vol. 48 (13), p. 3795-3801
Journal article
2009

3D chip stacking using planarized carbon nanotubes as through-silicon-vias

Kjell Jeppson, Teng Wang, Johan Liu et al
Swedish System on Chip Conference
Conference contribution
2009

Through silicon vias filled with planarized carbon nanotube bundles

Teng Wang, Kjell Jeppson, Niklas Olofsson et al
Nanotechnology. Vol. 20 (48), p. 485203-
Journal article
2008

Increasing student examination rate by use of weekly home assignments

Kjell Jeppson
European Workshop on Microelectronics Education. Vol. (EWME 2008)
Paper in proceedings
2008

Microelectronics based on Linear Relationships

Kjell Jeppson
European Workshop on Microelectronics Education. Vol. (EWME 2008)
Paper in proceedings
2008

Noise Interaction Between Power Distribution Grids and Substrate

Daniel Andersson, Simon Kristiansson, Lars Svensson et al
Proceedings of Intl Symp. on Quality Electronic Design (ISQED), p. 84-90
Paper in proceedings
2008

A New Master's Program in Integrated Electronic System Design

Kjell Jeppson, Lena Peterson, Lars Svensson et al
European Workshop on Microelectronics Education. Vol. EWME 2008 (Budapest)
Paper in proceedings
2007

Evaluation of Active Cancellation of Substrate-Noise in Mixed-Signal ICs

Zargham Baghchehsaraei, Simon Kristiansson, Fredrik Ingvarson et al
IEEE Norchip Conference. Vol. 2007
Paper in proceedings
2007

Exposed Datapath for Efficient Computing

Magnus Björk, Magnus Själander, Lars Svensson et al
2007 HiPEAC Workshop on Reconfigurable Computing
Paper in proceedings
2007

Evaluation of Using Active Circuitry for Substrate Noise Suppression

Rashid Farivar, Simon Kristiansson, Fredrik Ingvarson et al
ACM Great Lakes Symposium on VLSI (GLSVLSI), p. 449-452
Paper in proceedings
2007

A Student-Oriented Course in Digital VLSI Design

Kjell Jeppson
Microelectronic Systems Education, 2007 IEEE International Conference on, p. 57-58
Paper in proceedings
2007

A Compact Resistance Model of an Array of Substrate Contacts for Applications in Noise Coupling Analysis

Simon Kristiansson, Fredrik Ingvarson, Kjell Jeppson
Swedish System on Chip Conference
Conference contribution
2007

Compact Spreading Resistance Model for Rectangular Contacts on Uniform and Epitaxial Substrates

Simon Kristiansson, Fredrik Ingvarson, Kjell Jeppson
IEEE Transactions on Electron Devices. Vol. 54 (9), p. 2531-2536
Journal article
2006

Properties and Modeling of Ground Structures for Reducing Substrate Noise Coupling in ICs

Simon Kristiansson, Fredrik Ingvarson, Kjell Jeppson
IEEE International Symposium on Circuits and Systems
Paper in proceedings
2006

MOSFET Modelling for the new millenium

Kjell Jeppson
European Workshop on Microelectronics Education, p. 55-58
Paper in proceedings
2006

Exposed Datapath for Efficient Computing

Magnus Björk, Magnus Själander, Lars Svensson et al
Report
2006

gm/ID-related MOSFET modeling for analog circuit design

Roger Malmberg, Kjell Jeppson, Lena Peterson
European Workshop on Microelectronics Education, p. 51-54
Paper in proceedings
2006

Substrate Noise Reduction Using Active Circuitry

Rashid Farivar, Simon Kristiansson, Fredrik Ingvarson et al
Swedish System on Chip Conference
Conference contribution
2006

A High-Frequency Extension of a Surface-Potential-Based Substrate Model for Noise Coupling Analysis

Nebojsa Simic, Fredrik Ingvarson, Simon Kristiansson et al
International Conference on Microelectronics
Journal article
2006

gm/IDS-related MOSFET Modelling for Analog Circuit Design

Roger Malmberg, Kjell Jeppson, Lena Peterson
Swedish System-on-Chip Conference. Vol. SSoCC (2006)
Conference contribution
2006

Lab on the Web - Looking at Different Ways of Experiencing Electronic Experiments

Per Lundgren, Kjell Jeppson, Åke Ingerman
International Journal of Engineering Education. Vol. 22 (2), p. 308-314
Journal article
2006

Piece-wise modelling - bringing the essentials of MOSFET modelling to a new student generation

Kjell Jeppson
24th Norchip Conference, 2006; Linkoping; Sweden; 20 November 2006 through 21 November 2006, p. 99-102
Paper in proceedings
2006

MOSFET Modelling for Non-Physics Undergraduate Students in the First Decade of the New Millenium

Kjell Jeppson
Swedish System-on-Chip Conference. Vol. SSoCC (2006)
Conference contribution
2005

A comparison of the exact and an approximate solution for the resistance between two coplanar circular discs

Simon Kristiansson, Shiva P. Kagganti, Fredrik Ingvarson et al
Solid-State Electronics. Vol. 49 (2), p. 275-277
Journal article
2005

Modeling of Rectangular Contacts for Noise Coupling Analysis in Homogeneous Substrates

Simon Kristiansson, Fredrik Ingvarson, Kjell Jeppson
23rd Norchip Conference, Oulu, Finland
Paper in proceedings
2005

A Surface Potential Model for Predicting Substrate Noise Coupling in Integrated Circuits

Simon Kristiansson, Fredrik Ingvarson, Shiva P. Kagganti et al
IEEE Journal of Solid-State Circuits. Vol. 40 (9), p. 1797-1803
Journal article
2005

Influence of Guard Bands on Substrate Noise Coupling

Simon Kristiansson, Fredrik Ingvarson, Kjell Jeppson
Proceedings of the Swedish System-on-Chip Conference 2005
Conference contribution
2004

A Surface Potential Model for Predicting Substrate Noise Coupling in Integrated Circuits

Simon Kristiansson, Fredrik Ingvarson, Shiva P. Kagganti et al
Proceedings of the IEEE 2004 Custom Integrated Circuits Conference, CICC; Orlando, FL; United States; 3 October 2004 through 6 October 2004, p. 497-500
Paper in proceedings
2004

Resistance Modeling in 1D, 2D, and 3D for Substrate Networks

Shiva P. Kagganti, Simon Kristiansson, Fredrik Ingvarson et al
Physica Scripta. Vol. T114, p. 217-222
Journal article
2004

SHARING ONLINE LABORATORIES AND THEIR COMPONENTS - A new learning experience

Kjell Jeppson, Per Lundgren, Jesus Del Alamo et al
5th European Workshop on Microelectronics Education (EWME 2004). Vol. Lausanne (Switzerland)
Paper in proceedings
2004

Att dela online-resurser

Kjell Jeppson, Per Lundgren, Jesus Del Alamo
Netlearning 2002. Vol. Ronneby (Sverige)
Conference contribution
2004

Theory of a room-temperature silicon quantum dot device as a sensitive electrometer

J Vincent, V. Narayan, H. Pettersson et al
Journal of Applied Physics. Vol. 95 (1), p. 323-326
Journal article
2003

FlexSoC: Combining Flexibility and Efficiency in SoC Designs

John Hughes, Kjell Jeppson, Per Larsson-Edefors et al
Proceedings of 21st Norchip Conference. Vol. Riga, Latvia, p. 52-55
Paper in proceedings
2003

Resistance Modelling in 1D, 2D, and 3D for Substrate Networks

Shiva P. Kagganti, Simon Kristiansson, Fredrik Ingvarson et al
Nordic Semiconductor Meeting, Tampere, Finland
Paper in proceedings
2003

An Accurate Pi Resistor Network for Substrate Coupling Estimation

Shiva P. Kagganti, Simon Kristiansson, Fredrik Ingvarson et al
21st Norchip Conference, Riga, Latvia
Paper in proceedings
2003

Extraction of the base and emitter resistances in bipolar transistors using an accurate base resistance model

Fredrik Ingvarson, Martin Linder, Kjell Jeppson
IEEE Transactions on Semiconductor Manufacturing. Vol. 16 (2), p. 228-232
Journal article
2003

Substrate Resistance Modelling in One, Two and Three Dimensions

Shiva P. Kagganti, Simon Kristiansson, Fredrik Ingvarson et al
Swedish System-on-Chip Conference, Eskilstuna
Conference contribution
2003

Substrate Resistance Modeling for Noise Coupling Analysis

Simon Kristiansson, Shiva P. Kagganti, Ewert Tony et al
International Conference on Microelectronics Test Structures, Monterey, California, USA
Paper in proceedings
2002

Extraction of the base and emitter resistances in bipolar transistors using an accurate base resistance model

Fredrik Ingvarson, Martin Linder, Kjell Jeppson
Proceedings of the 2002 IEEE International Conference on Microelectronic Test Structures, p. 71-75
Paper in proceedings
2001

A new test structure for parasitic resistance extraction in bipolar transistors

Martin Linder, Fredrik Ingvarson, Kjell Jeppson et al
Proceedings of the 2001 IEEE International Conference on Microelectronic Test Structures, p. 25-30
Paper in proceedings
2001

A procedure for characterizing the BJT base resistance and Early voltages utilizing a dual base transistor test structure

Fredrik Ingvarson, Martin Linder, Kjell Jeppson et al
Proceedings of the 2001 IEEE International Conference on Microelectronic Test Structures, p. 31-36
Paper in proceedings
2000

Extraction of the intrinsic base region sheet resistance in bipolar transistors

Fredrik Ingvarson, Martin Linder, Kjell Jeppson et al
Proceedings of the 2000 IEEE Bipolar/BiCMOS Circuits and Technology Meeting, p. 184-186
Paper in proceedings
2000

Extraction of emitter and base series resistances of bipolar transistors from a single DC measurement

Martin Linder, Fredrik Ingvarson, Kjell Jeppson et al
IEEE Transactions on Semiconductor Manufacturing. Vol. 13 (2), p. 119-126
Journal article
2000

On DC modeling of the base resistance in bipolar transistors

Martin Linder, Fredrik Ingvarson, Kjell Jeppson et al
Solid-State Electronics. Vol. 44 (8), p. 1411-1418
Journal article
1999

Stress and recovery transients in bipolar transistors and MOS structures

Fredrik Ingvarson, Lars-Åke Ragnarsson, Per Lundgren et al
Proceedings of the 1999 IEEE International Conference on Microelectronic Test Structures, p. 173-178
Paper in proceedings
1999

A new procedure for extraction of series resistances for bipolar transistors from DC measurements

Martin Linder, Fredrik Ingvarson, Kjell Jeppson et al
Proceedings of the 1999 IEEE International Conference on Microelectronic Test Structures, p. 147-151
Paper in proceedings
1998

Parameter extraction for bipolar transistors

Fredrik Ingvarson, Kjell Jeppson
Microelectronic Engineering. Vol. 40 (3-4), p. 187-94
Journal article
1998

Static Characterization and parameter Extraction in MOS Transistors

Kjell Jeppson
Microelectronic Engineering. Vol. 40 (3-4), p. 181-186
Journal article
1998

A new direct extraction algorithm for intrinsic Gummel-Poon BJT model parameters

Fredrik Ingvarson, Kjell Jeppson
Proceedings of the 1998 IEEE International Conference on Microelectronic Test Structures, p. 159-164
Paper in proceedings
1997

Test chip and data considerations for MOS parameter extraction

Peter R. Karlsson, Kjell Jeppson
Proceedings of the IEEE International Conference on Microelectronic Test Structures ICMTS. Vol. 1997 (17-20 March 1997)
Paper in proceedings
1996

An efficient method for determining threshold voltage, series resistance and effective geometry of MOS transistors

Peter R. Karlsson, Kjell Jeppson
IEEE Transactions on Semiconductor Manufacturing. Vol. 9 (2), p. 215 - 222
Journal article
1996

A new method of determining the effective channel width and its dependence on the gate voltage

Peter R. Karlsson, Kjell Jeppson, Anders Bogren
Proceedings of the IEEE International Conference on Microelectronic Test Structures ICMTS. Vol. 1996 (25-28 March 1996)
Paper in proceedings
1996

Applications of aluminium nitride films deposited by reactive sputtering to silicon-on-insulator materials

Stefan Bengtsson, Mats Bergh, Manolis Choumas et al
Japanese Journal Of Applied Physics Part 1-Regular Papers Short Notes & Review Papers. Vol. 35 (8), p. 4175-4181
Journal article
1994

Direct extraction of MOS transistor model parameters

Peter R. Karlsson, Kjell Jeppson
Analog Integrated Circuits and Signal Processing. Vol. 5 (3), p. 199-212
Journal article
1994

Analytical extraction method for submicron MOS transistor model parameters in the linear region

Peter R. Karlsson, Kjell Jeppson
IEE Proceedings: Circuits, Devices and Systems. Vol. 141 (6), p. 457 - 461
Journal article
1994

A direct method to extract effective geometries and series resistances of MOS transistors

Peter R. Karlsson, Kjell Jeppson
Proceedings of the International Conference on Microelectronic Test Structures ICMTS. Vol. 1994 (22-25 March 1994)
Paper in proceedings
1993

Single Event Upset Behavior of CMOS Static RAM Cells

Kjell Jeppson, Udo Lieneweg, Martin G. Buehler
JPL Technical Report Server. Vol. 1993
Magazine article
1993

Comments on "A module generator for optimized CMOS buffers"

Nils Hedenstierna, Kjell Jeppson
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. Vol. 12 (1), p. 180-181
Magazine article
1993

A direct extraction algorithm for a submicron MOS transistor model

Peter R. Karlsson, Kjell Jeppson
Proceedings of the International Conference on Microelectronic Test Structures ICMTS. Vol. 1993 (22-25 March 1993)
Paper in proceedings
1993

Formal definitions of edge-based geometric design rules

Nils Hedenstierna, Sven Christensson, Kjell Jeppson
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. Vol. 12 (1), p. 59-69
Journal article
1993

The halo algorithm-an algorithm for hierarchical design of rule checking of VLSI circuits

Nils Hedenstierna, Kjell Jeppson
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. Vol. 12 (2), p. 265 - 272
Journal article
1992

Extraction of series-resistance-independent MOS transistor model parameters

Peter R. Karlsson, Kjell Jeppson
IEEE Electron Device Letters. Vol. 13 (11), p. 581-583
Journal article
1992

A parallel hierarchical design rule checker

Nils Hedenstierna, Kjell Jeppson
[3rd] European Conference on Design Automation. Vol. 1992, p. 142-146
Paper in proceedings
1992

An efficient parameter extraction algorithm for MOS transistor models

Peter R. Karlsson, Kjell Jeppson
IEEE Transactions on Electron Devices. Vol. 39 (9), p. 2070 - 2076
Journal article
1992

An analytical strategy for fast extraction of MOS transistor DC parameters applied to the SPICE M)53 and BSIM models

Peter R. Karlsson, Kjell Jeppson
Proceedings of the International Conference on Microelectronic Test Structures ICMTS. Vol. 1992 (16-19 March 1992)
Paper in proceedings
1990

A fast method of parameter extraction for MOS transistors

Peter R. Karlsson, Kjell Jeppson
European Solid State Device Research Conference ESSDERC. Vol. 1990 (10-13 Sept. 1990)
Paper in proceedings
1989

The Use of Inverse Layout Trees for Hierarchical Design Rule Checking

Nils Hedenstierna, Kjell Jeppson
26th Conference on Design Automation. Vol. 1989 (25-29 June 1989), p. 508-512
Paper in proceedings
1988

The Use of Inverse Layout Trees for Hierarchical Design Rule Checking

Nils Hedenstierna, Kjell Jeppson
IEEE International Conference on Computer-Aided Design ICCAD. Vol. 1988, p. 534-537
Paper in proceedings
1987

CMOS Circuit Speed and Buffer Optimization

Kjell Jeppson, Nils Hedenstierna
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. Vol. 6 (2), p. 270 - 281
Journal article
1977

Negative bias stress of MOS devices at high electric fields and degradation of MNOS devices

Kjell Jeppson, Christer Svensson
Journal of Applied Physics. Vol. 48 (5), p. 2004-2014
Journal article
1976

The effects of impurity redistribution of the subthreshold leakage current in CMOS n-channel transistors

Kjell Jeppson, James Gates
Solid-State Electronics. Vol. 19 (1), p. 83-85
Journal article
1976

Unintentional writing of a FAMOS memory device during reading

Kjell Jeppson, Christer Svensson
Solid-State Electronics. Vol. 19 (6), p. 455-457
Journal article
1975

Influence of the channel width on the threshold voltage modulation in MOSFETs

Kjell Jeppson
Electronics Letters. Vol. 11 (14), p. 297-299
Journal article
1973

A content-addressable memory cell with MNOS transistors

Kjell Jeppson, Göran Peterson, Gunnar Carlstedt
IEEE Journal of Solid-State Circuits. Vol. 8 (5), p. 338 - 343
Journal article

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Showing 1 research projects

2010–2013

Thermal management with carbon nanotube architectures (THEMA-CNT)

Kjell Jeppson Electronics Material and Systems
European Commission (FP7)

There might be more projects where Kjell Jeppson participates, but you have to be logged in as a Chalmers employee to see them.