Test chip and data considerations for MOS parameter extraction
Paper in proceeding, 1997
This paper presents an investigation of principles for test chip design and data point selection for MOS parameter extraction methods using a low number of data points. Variations in extracted parameter values for different combinations and numbers of data points are studied experimentally. The influences on the standard deviations of V/sub T/, /spl beta/, /spl theta/, R/sub S/, /spl Delta/W and /spl Delta/L of different data point selections and device combinations are studied using synthetic data with multiplicative noise.
Parameter extraction
Data mining
Voltage
Noise measurement
Geometry
MOSFETs
Electronic equipment testing
Semiconductor device measurement
Circuit noise
Chip scale packaging
Author
Peter R. Karlsson
Department of Solid State Electronics
Kjell Jeppson
Department of Solid State Electronics
Department of Microelectronics and Nanoscience
Proceedings of the IEEE International Conference on Microelectronic Test Structures ICMTS
Vol. 1997 17-20 March 1997
0-7803-3243-1 (ISBN)
Subject Categories
Electrical Engineering, Electronic Engineering, Information Engineering
ISBN
0-7803-3243-1