Test chip and data considerations for MOS parameter extraction
Paper i proceeding, 1997

This paper presents an investigation of principles for test chip design and data point selection for MOS parameter extraction methods using a low number of data points. Variations in extracted parameter values for different combinations and numbers of data points are studied experimentally. The influences on the standard deviations of V/sub T/, /spl beta/, /spl theta/, R/sub S/, /spl Delta/W and /spl Delta/L of different data point selections and device combinations are studied using synthetic data with multiplicative noise.

Parameter extraction

Data mining


Noise measurement



Electronic equipment testing

Semiconductor device measurement

Circuit noise

Chip scale packaging


Peter R. Karlsson

Institutionen för fasta tillståndets elektronik

Kjell Jeppson

Institutionen för fasta tillståndets elektronik

Institutionen för mikroelektronik och nanovetenskap

Proceedings of the IEEE International Conference on Microelectronic Test Structures ICMTS

Vol. 1997 17-20 March 1997


Elektroteknik och elektronik