Electrical Interconnects Made of Carbon Nanotubes: Applications in 3D Chip Stacking
Paper in proceedings, 2012

High density electronics integration at the system level, supported by advanced packaging solutions, is expected to be the driving force for the future down-scaling of semiconductor electronics. One recent focus in the field of electronic packaging is the use of through-silicon-vias (TSVs) to form three-dimensional (3D) integration. A central task in developing 3D chip integration is to build reliable and efficient 3D electrical interconnects for signal transfer and power distribution among the stacked layers. Carbon nanotubes (CNTs) are proposed to be a promising material to build future interconnects due to their many attractive electrical and mechanical properties. This paper reviews the state-of-art in CNT integration technology, with a focus on the application of 3D chip stacking TSV interconnects. The simplicity and manufacturability of fabricating CNT TSVs presented in this paper indicate a great application potential of CNTs as an interconnection material in future 3D integrated electronics.

Author

Di Jiang

Chalmers, Applied Physics, Electronics Material and Systems Laboratory

Kjell Jeppson

Chalmers, Applied Physics, Electronics Material and Systems Laboratory

Johan Liu

Chalmers, Applied Physics, Electronics Material and Systems Laboratory

IMAPS Nordic Annual Conference Proceedings 2012, Helsingor, 2 - 4 September 2012

150-159

Subject Categories

Other Electrical Engineering, Electronic Engineering, Information Engineering

ISBN

978-162276316-0

More information

Created

10/7/2017