The Use of Inverse Layout Trees for Hierarchical Design Rule Checking
Paper in proceeding, 1989
High performance computing
Geometry
Wires
Solid state circuits
Machinery
Tree data structures
Very large scale integration
Distributed computing
Author
Nils Hedenstierna
Department of Solid State Electronics
Kjell Jeppson
Department of Solid State Electronics
Department of Microelectronics and Nanoscience
26th Conference on Design Automation
0738-100X (ISSN)
Vol. 1989 25-29 June 1989 508-5120-89791-310-8 (ISBN)
Subject Categories
Computer and Information Science
Electrical Engineering, Electronic Engineering, Information Engineering
ISBN
0-89791-310-8