New algorithms for increased efficiency in hierarchical design rule checking

Journal article, 1987

This paper presents two new algorithms that make hierarchical geometric design rule checkers more efficient. The first is a method to reduce the number of design rules to be checked when a subcell interact with layout outside the subcell. The second method checks large array of cells (PLA, RAM, ROM, datapaths) in a very efficient way. It could also be used to validate certain types of module generators. These algorithms have been implemented in a program using corner-based rules and an adaptive quad tree as data structure.