Through silicon vias filled with planarized carbon nanotube bundles
Journal article, 2009

The feasibility of using carbon nanotube (CNT) bundles as the fillers of through silicon vias (TSVs) has been demonstrated. CNT bundles are synthesized directly inside TSVs by thermal chemical vapor deposition (TCVD). The growth of CNTs in vias is found to be highly dependent on the geometric dimensions and arrangement patterns of the vias at atmospheric pressure. The CNT-Si structure is planarized by a combined lapping and polishing process to achieve both a high removal rate and a fine surface finish. Electrical tests of the CNT TSVs have been performed and their electrical resistance was found to be in the few hundred ohms range. The reasons for the high electrical resistance have been discussed and possible methods to decrease the electrical resistance have been proposed.

Author

Teng Wang

Chalmers, Applied Physics, Electronics Material and Systems Laboratory

Kjell Jeppson

Chalmers, Applied Physics, Physical Electronics

Niklas Olofsson

University of Gothenburg

Eleanor E B Campbell

University of Gothenburg

Johan Liu

Chalmers, Applied Physics, Electronics Material and Systems Laboratory

Nanotechnology

0957-4484 (ISSN) 1361-6528 (eISSN)

Vol. 20 48 485203-

Subject Categories

Electrical Engineering, Electronic Engineering, Information Engineering

DOI

10.1088/0957-4484/20/48/485203

More information

Created

10/7/2017