Evaluation of Power Cut-Off Techniques in the Presence of Gate Leakage

Paper in proceeding, 2004

We consider gate leakage next to subthreshold leakage currents in power-saving techniques for future CMOS circuits. Two recently introduced power cut-off techniques are analyzed and compared with respect to the total leakage current using Berkeley PTM. The results show that the efficiency of techniques having logic circuits alternately connected to external supply and ground can drastically de,grade when gate tunneling currents become significant.