Showing 15 publications
Overdrive Power-Gating Techniques for Total Power Minimization
Capturing Process-Voltage-Temperature (PVT) Variations in Architectural Static Power Modeling for SRAM Arrays
Current Probing Methodology for Static Power Extraction in Sub-90nm CMOS Circuits
Leakage-Conscious Architecture-Level Power Estimation for Partitioned and Power-Gated SRAM Arrays
High-Accuracy Architecture-Level Power Estimation for Partitioned Arrays in a 65-nm CMOS BPTM Process
Parameterizable Architecture-Level SRAM Power Model Using Circuit-Simulation Backend for Leakage Calibration
Architecture-Level Power Estimation and Scaling Trends for SRAM Arrays
Static Power Reduction and Estimation in CMOS Circuits Considering Emerging Leakage Mechanisms
A Low-Leakage Twin-Precision Multiplier Using Reconfigurable Power Gating
A Power Cut-Off Technique for Gate Leakage Suppression
Evaluation of Power Cut-Off Techniques in the Presence of Gate Leakage
A Comparison of Power Cut-Off Techniques Employed for Ripple Carry Adders in the Presence of Gate Leakage
Sleep-Mode Circuit Techniques in the Presence of Gate Leakage
A Gate Leakage Reduction Strategy for Future CMOS Circuits
An Investigation of Gate Leakage for Future CMOS Circuits
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