A Gate Leakage Reduction Strategy for Future CMOS Circuits

Paper in proceeding, 2003

We show that a technique previously introduced for subthreshold leakage reduction can be effectively used to reduce gate leakage power dissipation in future CMOS circuits operating in stand-by mode. The technique gave one order of magnitude gate leakage savings with a certain input pattern for the evaluated two-input NAND gate. Also, we make a detailed analysis of mechanisms causing different direct oxide tunneling currents that will contribute to gate leakage power dissipation in future CMOS circuits.