A Gate Leakage Reduction Strategy for Future CMOS Circuits
Paper in proceedings, 2003

We show that a technique previously introduced for subthreshold leakage reduction can be effectively used to reduce gate leakage power dissipation in future CMOS circuits operating in stand-by mode. The technique gave one order of magnitude gate leakage savings with a certain input pattern for the evaluated two-input NAND gate. Also, we make a detailed analysis of mechanisms causing different direct oxide tunneling currents that will contribute to gate leakage power dissipation in future CMOS circuits.

Author

Mindaugas Drazdziulis

Chalmers, Department of Computer Engineering, Integrated Electronic Systems

Per Larsson-Edefors

Chalmers, Department of Computer Engineering, Integrated Electronic Systems

Proceedings of the 29th European Solid-State Circuits Conference, ESSCIRC 2003, Estoril, 16-18 September 2003

1930-8833 (ISSN)

317-320

Subject Categories

Other Electrical Engineering, Electronic Engineering, Information Engineering

DOI

10.1109/ESSCIRC.2003.1257136

ISBN

0-7803-7995-0

More information

Created

10/7/2017