High-Accuracy Architecture-Level Power Estimation for Partitioned Arrays in a 65-nm CMOS BPTM Process
Paper in proceeding, 2007
Author
Minh Quang Do
Chalmers, Computer Science and Engineering (Chalmers), Computer Engineering (Chalmers)
Per Larsson-Edefors
Chalmers, Computer Science and Engineering (Chalmers), Computer Engineering (Chalmers)
Mindaugas Drazdziulis
Chalmers, Computer Science and Engineering (Chalmers), Computer Engineering (Chalmers)
Proceedings of the 10th Euromicro Conference on Digital System Design, Architecture, Methoods and Tools (DSD 2007)
Subject Categories
Other Electrical Engineering, Electronic Engineering, Information Engineering