Mindaugas Drazdziulis

Visar 15 publikationer

2007

Overdrive Power-Gating Techniques for Total Power Minimization

Mindaugas Drazdziulis, Per Larsson-Edefors, Lars Svensson
IEEE Computer Society Annual Symposium on VLSI
Paper i proceeding
2007

Capturing Process-Voltage-Temperature (PVT) Variations in Architectural Static Power Modeling for SRAM Arrays

Minh Quang Do, Per Larsson-Edefors, Mindaugas Drazdziulis
Rapport
2007

Current Probing Methodology for Static Power Extraction in Sub-90nm CMOS Circuits

Minh Quang Do, Per Larsson-Edefors, Mindaugas Drazdziulis
Rapport
2007

Leakage-Conscious Architecture-Level Power Estimation for Partitioned and Power-Gated SRAM Arrays

Minh Quang Do, Mindaugas Drazdziulis, Per Larsson-Edefors et al
8th International Symposium on Quality Electronic Design (ISQED’07), p. 185 - 191
Paper i proceeding
2007

High-Accuracy Architecture-Level Power Estimation for Partitioned Arrays in a 65-nm CMOS BPTM Process

Minh Quang Do, Per Larsson-Edefors, Mindaugas Drazdziulis
Proceedings of the 10th Euromicro Conference on Digital System Design, Architecture, Methoods and Tools (DSD 2007)
Paper i proceeding
2006

Parameterizable Architecture-Level SRAM Power Model Using Circuit-Simulation Backend for Leakage Calibration

Minh Quang Do, Mindaugas Drazdziulis, Per Larsson-Edefors et al
International Symposium on Quality Electronic Design (ISQED)
Paper i proceeding
2006

Architecture-Level Power Estimation and Scaling Trends for SRAM Arrays

Minh Quang Do, Mindaugas Drazdziulis, Per Larsson-Edefors
Swedish System-on-Chip Conference
Konferensbidrag (offentliggjort, men ej förlagsutgivet)
2005

A Low-Leakage Twin-Precision Multiplier Using Reconfigurable Power Gating

Magnus Själander, Mindaugas Drazdziulis, Per Larsson-Edefors et al
IEEE International Symposium on Circuits and Systems, p. 1654-7
Paper i proceeding
2004

A Power Cut-Off Technique for Gate Leakage Suppression

Mindaugas Drazdziulis, Per Larsson-Edefors, Daniel Eckerbert et al
European Solid-State Circuits Conference (ESSCIRC), p. 171-174
Paper i proceeding
2004

Evaluation of Power Cut-Off Techniques in the Presence of Gate Leakage

Mindaugas Drazdziulis, Per Larsson-Edefors
2004 IEEE International Symposium on Cirquits and Systems - Proceedings; Vancouver, BC; Canada; 23 May 2004 through 26 May 2004, p. II745-II748
Paper i proceeding
2004

A Comparison of Power Cut-Off Techniques Employed for Ripple Carry Adders in the Presence of Gate Leakage

Mindaugas Drazdziulis, Per Larsson-Edefors
Swedish System-on-Chip Conference
Konferensbidrag (offentliggjort, men ej förlagsutgivet)
2004

Sleep-Mode Circuit Techniques in the Presence of Gate Leakage

Mindaugas Drazdziulis
Licentiatavhandling
2003

A Gate Leakage Reduction Strategy for Future CMOS Circuits

Mindaugas Drazdziulis, Per Larsson-Edefors
Proceedings of the 29th European Solid-State Circuits Conference, ESSCIRC 2003, Estoril, 16-18 September 2003, p. 317-320
Paper i proceeding
2003

An Investigation of Gate Leakage for Future CMOS Circuits

Mindaugas Drazdziulis, Per Larsson-Edefors
Proceedings of the Swedish System-on-Chip Conference
Konferensbidrag (offentliggjort, men ej förlagsutgivet)

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