A Power Cut-Off Technique for Gate Leakage Suppression
Paper i proceeding, 2004

Gate leakage power dissipation is predicted to overtake subthreshold leakage power within the next few years thus adding further problems for designers trying to meet a strict power budget. In this paper a power cut-off technique is proposed, which in steep mode suppresses not only subthreshold leakage but also gate leakage. The proposed technique displays a combination of low total leakage power and short wake-up time.

Författare

Mindaugas Drazdziulis

Chalmers, Institutionen för datorteknik, Integrerade elektroniksystem

Per Larsson-Edefors

Chalmers, Institutionen för datorteknik, Integrerade elektroniksystem

Daniel Eckerbert

Chalmers, Institutionen för datorteknik, Integrerade elektroniksystem

Henrik Eriksson

Chalmers, Institutionen för datorteknik, Integrerade elektroniksystem

European Solid-State Circuits Conference (ESSCIRC)

171-174

Ämneskategorier

Data- och informationsvetenskap

DOI

10.1109/ESSCIR.2004.1356645