Static Power Reduction and Estimation in CMOS Circuits Considering Emerging Leakage Mechanisms
Doktorsavhandling, 2006

Due to semiconductor technology advancements, the static power dissipation caused by leakage currents in CMOS circuits is growing at a much faster rate than dynamic power; the dominant power component. As a result, controlling and limiting static power becomes as crucial as controlling dynamic power. Out of a number of introduced circuit techniques addressing the leakage issue, power gating shows the most promising results, achieving 100x leakage reduction. Several power-gating techniques have been proposed to date, however, no single one is ideal for all design scenarios. In order to minimize power and maximize performance, selecting the most appropriate power-gating technique for a given design scenario is of paramount importance. This thesis gives guidelines on how to choose the appropriate power-gating technique, depending on design parameters such as performance, power, area, and logic circuit behavior. When large logic blocks are idle for long periods of time and do not need to be activated quickly, power gating employing power switch overdrive should be used. The total power in sleep mode is often minimized when the overdrive voltage is at the maximum level allowed by the semiconductor technology. To deal with the issue of process parameter variations, when generating maximum overdrive voltages, a new generator is proposed. Circuit-level remedies to emerging and harmful leakage mechanisms---most notably gate leakage---are also discussed. Existing power-gating techniques are re-evaluated and compared, with an emphasis on total (subthreshold and gate) leakage power. Subsequently, a new power-gating technique for gate-leakage suppression is proposed. Finally, an approach to accurately capture and characterize emerging leakage mechanisms in SRAM arrays for accurate high-level modeling is proposed.



wake-up time

power gating

gate leakage


09.00 HA2, Hörsalsvägen
Opponent: Professor Doris Schmitt-Landsiedel, Technische Universität Munchen


Mindaugas Drazdziulis

Chalmers, Data- och informationsteknik, Datorteknik

A Low-Leakage Twin-Precision Multiplier Using Reconfigurable Power Gating

IEEE International Symposium on Circuits and Systems,; (2005)p. 1654-7

Paper i proceeding

A Power Cut-Off Technique for Gate Leakage Suppression

European Solid-State Circuits Conference (ESSCIRC),; (2004)p. 171-174

Paper i proceeding

A Gate Leakage Reduction Strategy for Future CMOS Circuits

Proceedings of the 29th European Solid-State Circuits Conference, ESSCIRC 2003, Estoril, 16-18 September 2003,; (2003)p. 317-320

Paper i proceeding

Evaluation of Power Cut-Off Techniques in the Presence of Gate Leakage

2004 IEEE International Symposium on Cirquits and Systems - Proceedings; Vancouver, BC; Canada; 23 May 2004 through 26 May 2004,; (2004)p. II745-II748

Paper i proceeding

Parameterizable Architecture-Level SRAM Power Model Using Circuit-Simulation Backend for Leakage Calibration

International Symposium on Quality Electronic Design (ISQED),; (2006)

Paper i proceeding





Doktorsavhandlingar vid Chalmers tekniska högskola. Ny serie: 2536

Technical report D - Department of Computer Science and Engineering, Chalmers University of Technology and Göteborg University: 23

09.00 HA2, Hörsalsvägen

Opponent: Professor Doris Schmitt-Landsiedel, Technische Universität Munchen