Current Probing Methodology for Static Power Extraction in Sub-90nm CMOS Circuits
Rapport, 2007

Static power dissipation is steadily increasing, calling for the full attention of circuit designers. As a result of scaling, static currents are flowing in a very complex manner through digital circuits. For example, static currents flow through the interface between CMOS gates, which is in contrast to when only subthreshold leakage was considered. It follows that the methodology for probing circuits for current measurements during simulation has become complex.We explain how to account, in circuit simulation, for static currents in CMOS circuits in general, and show the detailed probing strategy for a number of central gates: a NAND gate, an SRAM cell and the full adder.


Deep Submicron

Power Estimation

SRAM Power Modeling



Minh Quang Do

Chalmers, Data- och informationsteknik, Datorteknik

Per Larsson-Edefors

Chalmers, Data- och informationsteknik, Datorteknik

Mindaugas Drazdziulis

Chalmers, Data- och informationsteknik, Datorteknik


Annan elektroteknik och elektronik



Technical report L - Department of Computer Science and Engineering, Chalmers University of Technology and Göteborg University

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