Leakage-Conscious Architecture-Level Power Estimation for Partitioned and Power-Gated SRAM Arrays
Paper i proceeding, 2007
We propose a methodology and power models for an accurate
high-level power estimation of physically partitioned
and power-gated SRAM arrays. The models offer accurate
estimation of both dynamic and leakage power, including
the power dissipation due to emerging leakage mechanisms
such as gate oxide tunneling, for partitioned arrays that deploy
data-retaining sleep techniques for leakage reduction.
Using the proposed methodology, dynamic, leakage and total
power of partitioned SRAM arrays can be estimated with
a 97% accuracy in comparison to the power obtained by
running full circuit-level simulations.
SRAM Power Modeling