Capturing Process-Voltage-Temperature (PVT) Variations in Architectural Static Power Modeling for SRAM Arrays
Rapport, 2007
We propose a modeling methodology, including power models, that
captures the dependence of leakage power on temperature and supply voltage
variations for accurate architectural-level power estimation of physically partitioned
and un-partitioned SRAMarrays. A simulation -based modeling approach
is used for temperature-aware leakage power estimation, while a physically-based
analytical approach is used for modeling the leakage dependence of memory cells
on supply voltage. By using the new power models, it is, for example, possible
to preserve our previously reported power estimation accuracy of 96% also in the
presence of temperature and voltage variations.
SRAM Power Modeling
VLSI
Deep Submicron
CMOS
Power Estimation