Improving Data Access Efficiency by Using Context-Aware Loads and Stores
Paper in proceedings, 2015

Memory operations have a significant impact on both performance and energy usage even when an access hits in the level-one data cache (L1 DC). Load instructions in particular affect performance as they frequently result in stalls since the register to be loaded is often referenced before the data is available in the pipeline. L1 DC accesses also impact energy usage as they typically require significantly more energy than a register file access. Despite their impact on performance and energy usage, L1 DC accesses on most processors are performed in a general fashion without regard to the context in which the load or store operation is performed. We describe a set of techniques where the compiler enhances load and store instructions so that they can be executed with fewer stalls and/or enable the L1 DC to be accessed in a more energy-efficient manner. We show that using these techniques can simultaneously achieve a 6% gain in performance and a 43% reduction in L1 DC energy usage.

Author

Alen Bardizbanyan

Chalmers, Computer Science and Engineering (Chalmers), Computer Engineering (Chalmers)

Magnus Själander

Uppsala University

David Whalley

Florida State University

Per Larsson-Edefors

Chalmers, Computer Science and Engineering (Chalmers), Computer Engineering (Chalmers)

SIGPLAN Notices (ACM Special Interest Group on Programming Languages)

0362-1340 (ISSN)

Vol. 50 5 27-36

Areas of Advance

Information and Communication Technology

Energy

Driving Forces

Sustainable development

Subject Categories

Computer Systems

DOI

10.1145/2670529.2754960

ISBN

978-1-4503-3257-6

More information

Latest update

2/28/2018