MIDAS: Model for IP-inclusive DFM assessment of system manufacturability
Paper in proceeding, 2014
Complex system implementations combined with the latest technology nodes allow us to implement hardware for versatile applications. The ever increasing demand for quick time-to-market has led to the widespread use of Intellectual Property (IP) in ASIC design methodologies. These developments, in addition to manufacturing limitations, make early prediction of manufacturability for complete systems challenging. We present MIDAS: a scalable, IP-inclusive model to predict system manufacturability. Results from applying MIDAS to an embedded processor system reveals that several useful insights can be gained towards realizing yield budgets for complex systems allowing quicker co-optimization of all implementation goals.
IP
DFM Metrics
ASIC
Manufacturability
Author
KASYAB PARMESH SUBRAMANIYAN
Chalmers, Computer Science and Engineering (Chalmers), Computer Engineering (Chalmers)
Per Larsson-Edefors
Chalmers, Computer Science and Engineering (Chalmers), Computer Engineering (Chalmers)
5th European Workshop on CMOS Variability, VARI 2014. Palma de Mallorca, SPAIN, SEP 29-OCT 01, 2014
Art. no. 6957079- 6957079
978-1-4799-5399-8 (ISBN)
Subject Categories
Computer and Information Science
DOI
10.1109/VARI.2014.6957079
ISBN
978-1-4799-5399-8