Methodology for Power-Aware Coherent Receiver Design
Paper in proceedings, 2013

We describe a methodology to design and evaluate DSP hardware for a coherent receiver. Important parameters that can be assessed include DSP power consumption and chip area.

Author

Tauseef Ahmad

Chalmers, Computer Science and Engineering (Chalmers)

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Yun Ai

Chalmers, Signals and Systems

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Pavithra Muralidharan

Chalmers, Computer Science and Engineering (Chalmers)

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Naga Vishnukanth Irukulapati

Chalmers, Signals and Systems, Communication and Antenna Systems, Communication Systems

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Pontus Johannisson

Chalmers, Microtechnology and Nanoscience (MC2), Photonics

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Henk Wymeersch

Chalmers, Signals and Systems, Communication and Antenna Systems, Communication Systems

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Erik Agrell

Chalmers, Signals and Systems, Communication and Antenna Systems, Communication Systems

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Per Larsson-Edefors

Chalmers, Computer Science and Engineering (Chalmers), Computer Engineering (Chalmers)

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Magnus Karlsson

Chalmers, Microtechnology and Nanoscience (MC2), Photonics

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Signal Processing in Photonic Communications

2162-2701 (ISSN)

SPT4D.4-

Signal Processing in Photonic Communications, SPPCom 2013
Rio Grande, Puerto Rico,

Areas of Advance

Information and Communication Technology

Subject Categories

Telecommunications

Communication Systems

DOI

10.1364/SPPCOM.2013.SPT4D.4

Publication data connected to DOI

More information

Latest update

12/13/2018

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