Methodology for Power-Aware Coherent Receiver Design
Paper in proceedings, 2013
We describe a methodology to design and evaluate DSP hardware for a coherent receiver. Important parameters that can be assessed include DSP power consumption and chip area.
Author
Tauseef Ahmad
Chalmers, Computer Science and Engineering (Chalmers)
Yun Ai
Chalmers, Signals and Systems
Pavithra Muralidharan
Chalmers, Computer Science and Engineering (Chalmers)
Naga Vishnukanth Irukulapati
Chalmers, Signals and Systems, Communication and Antenna Systems, Communication Systems
Pontus Johannisson
Chalmers, Microtechnology and Nanoscience (MC2), Photonics
Henk Wymeersch
Chalmers, Signals and Systems, Communication and Antenna Systems, Communication Systems
Erik Agrell
Chalmers, Signals and Systems, Communication and Antenna Systems, Communication Systems
Per Larsson-Edefors
Chalmers, Computer Science and Engineering (Chalmers), Computer Engineering (Chalmers)
Magnus Karlsson
Chalmers, Microtechnology and Nanoscience (MC2), Photonics
Signal Processing in Photonic Communications
2162-2701 (ISSN)
SPT4D.4-
Signal Processing in Photonic Communications, SPPCom 2013
Rio Grande, Puerto Rico,
Rio Grande, Puerto Rico,
Areas of Advance
Information and Communication Technology
Subject Categories
Telecommunications
Communication Systems
DOI
10.1364/SPPCOM.2013.SPT4D.4