Reconfigurable Instruction Decoding for a Wide-Control-Word Processor
Paper in proceedings, 2011

Fine-grained control through the use of a wide control word can lead to high instruction-level parallelism, but unless compressed the words require a large memory footprint. A reconfigurable fixed-length decoding scheme can be created by taking advantage of the fact that an application only uses a subset of the datapath for its execution. We present the first complete implementation of the FlexCore processor, integrating a wide-control-word datapath with a run-time reconfigurable instruction decompressor. Our evaluation, using three different EEMBC benchmarks, shows that it is possible to reach up to 35% speedup compared to a five-stage pipelined MIPS processor, assuming the same datapath units. In addition, our VLSI implementations show that this FlexCore processor offers up to 24% higher energy efficiency than the MIPS reference processor.

Author

Alen Bardizbanyan

Chalmers, Computer Science and Engineering (Chalmers), Computer Engineering (Chalmers)

Magnus Själander

Chalmers, Computer Science and Engineering (Chalmers), Computer Engineering (Chalmers)

Per Larsson-Edefors

Chalmers, Computer Science and Engineering (Chalmers), Computer Engineering (Chalmers)

Proceedings of Reconfigurable Architectures Workshop (RAW), IEEE International Parallel & Distributed Processing Symposium (IPDPS)

322-325

Areas of Advance

Information and Communication Technology

Driving Forces

Sustainable development

Innovation and entrepreneurship

Subject Categories

Other Electrical Engineering, Electronic Engineering, Information Engineering

DOI

10.1109/IPDPS.2011.155

ISBN

978-076954385-7

More information

Created

10/7/2017