Evaluating Branch Predictor Configurations for a MIPS-like Pipeline
Conference contribution, 2014

In this report, we investigate the implementation and efficiency of different types of branch predictors. A configurable VHDL model of a branch predictor unit, composed of a branch direction predictor and a branch target buffer, has been implemented. In order to make informed hardware decisions, different branch predictor configurations are simulated using the open source SimpleScalar simulator and the MiBench benchmark suite. The target architecture is a 7-stage 32-bit MIPS-based pipeline with two instruction fetch stages.

Author

Fredrik Brosser

Chalmers, Computer Science and Engineering (Chalmers)

Karthik Manchanahalli Rajendra Prasad

Chalmers, Computer Science and Engineering (Chalmers)

Alen Bardizbanyan

Chalmers, Computer Science and Engineering (Chalmers), Computer Engineering (Chalmers)

Per Larsson-Edefors

Chalmers, Computer Science and Engineering (Chalmers), Computer Engineering (Chalmers)

Swedish System-on-Chip Conference

Areas of Advance

Information and Communication Technology

Subject Categories

Computer Systems

More information

Created

10/7/2017