Hardware considerations for selection networks
Paper in proceeding, 2019

The selection operation is a central part of a soft-decision error-correction algorithm, which is important for high-performance communication networks. High symbol rates and power-dissipation limitations motivate hardware implementation as a comparator network. We use industry-standard tools to investigate VLSI hardware implementation of selection networks with up to 512 inputs. We find theoretical network depth and size to be poor predictors of hardware performance. In a 65-nm process, we find that our novel half-life network is competitive with and in some cases superior to Zazon-Ivry’s pairwise and odd/even selection networks, for delay, area, and energy per selection operation.


Kenneth Peter

Student at Chalmers

Lars Svensson

Chalmers, Computer Science and Engineering (Chalmers), Computer Engineering (Chalmers)

Christoffer Fougstedt

Chalmers, Computer Science and Engineering (Chalmers), Computer Engineering (Chalmers)

Per Larsson-Edefors

Chalmers, Computer Science and Engineering (Chalmers), Computer Engineering (Chalmers)

IEEE/IFIP International Conference on VLSI and System-on-Chip, VLSI-SoC

23248432 (ISSN) 23248440 (eISSN)

978-1-7281-3915-9 (ISBN)

IFIP International Conference on Very Large Scale Integration (VLSI-SoC)
Cuzco, Peru,

Energieffektiv och höghastighets-transmission i optisk fiber kommunikation

VINNOVA (2017-05228), 2018-01-01 -- 2019-12-31.

Subject Categories

Computer Engineering


Electrical Engineering, Electronic Engineering, Information Engineering

Areas of Advance

Information and Communication Technology



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