Lars Svensson
Showing 66 publications
A Review of IC Drivers for VCSELs in Datacom Applications
Unfolded SiBM BCH Decoders for High-Throughput Low-Latency Applications
Integration of BCH Encoder in SiGe Driver System
Scalable, Modular Feed-Forward Equalizer for Baseband Applications
VCSEL Integrated Circuit Drivers: A Review
RF PA Predistortion using Non-Linear RF-DACs
A 2x6b 8GS/s 17-24GHz I/Q RF-DAC based Transmitter in 22nm FDSOI CMOS
Hardware considerations for selection networks
ASIC Implementation of Time-Domain Digital Back Propagation for Coherent Receivers
A Framework for a Relative Real-Time Tracking System Based on Ultra-Wideband Technology
Custom versus Cell-Based ASIC Design for Many-Channel Correlators
Design Considerations and Evaluation of a High-Speed SAR ADC
Time-Domain Digital Back Propagation: Algorithm and Finite-Precision Implementation Aspects
A 3-GHz Reconfigurable 2/3-Level 96/48-Channel Cross-Correlator for Synthetic Aperture Radiometry
Instruction level energy model for the Adapteva Epiphany multi-core processor
Dynamic Equalizer Power Dissipation Optimization
A System-Level Mixed-Signal Design Course
Laptops in classroom interaction: Deconstructing the networked situation
Impact of Forward Error Correction on Energy Consumption of VCSEL-based Transmitters
A Novel Speculative Pseudo-Parallel \Delta\Sigma Modulator
On the Impact of Hardware Impairments on Massive MIMO
1.6 GHz Low-Power Cross-Correlator System Enabling Geostationary Earth Orbit Aperture Synthesis
3.6-GHz 0.2-mW/ch/GHz 65-nm Cross-Correlator for Synthetic Aperture Radiometry
Digital Cross-Correlators: Two Approaches
On-chip power supply noise and its implications on timing
A Single-Chip 64 Input Low Power High Speed Cross-Correlator for Space Application
On-chip Power Supply Noise and Its Implications on Timing
Supply Voltage Drop Study Considering On-Chip Self Inductance of a 32-bit Processor's Power Grid
FlexCore: Utilizing Exposed Datapath Control for Efficient Computing
Towards Supply-Grid-Based Derating of Timing Margins
High-Performance 64-input Cross-Correlator
Noise-Aware On-Chip Power Grid Considerations Using a Statistical Approach
Noise Interaction Between Power Distribution Grids and Substrate
Time-Domain Interconnect Characterisation Flow for Appropriate Model Segmentation
A New Master's Program in Integrated Electronic System Design
FlexCore: Utilizing Exposed Datapath Control for Efficient Computing
Toward a Systematic Sensitivity Analysis of On-Chip Power Grids Using Factor Analysis
Overdrive Power-Gating Techniques for Total Power Minimization
Exposed Datapath for Efficient Computing
Power-efficient, pulsed driving of capacitive loads to controllable voltage levels
Exposed Datapath for Efficient Computing
Interconnect Characterization Flow for Minimal-Segment Model Selection
Accounting for the Skin Effect during Repeater Insertion
Frequency-Dependent Effects in RLC Interconnects
On Skin Effect in On-Chip Interconnects
Method for reducing EMI and IR-drop in digital synchronous circuits
A Mixed-Mode Delay-Locked Loop Architecture
SYSTEM AND METHOD FOR IMPLEMENTING A SKEW-TOLERANT TRUE-SINGLE-PHASE-CLOCKING FLIP-FLOP
FlexSoC: Combining Flexibility and Efficiency in SoC Designs
Dual Threshold Voltage Circuits in the Presence of Resistive Interconnects
Using storage elements with multiple delay values to reduce current spikes in digital circuits
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classIC - Chalmers Lund Center for Advanced Semiconductor System Design