Design Considerations and Evaluation of a High-Speed SAR ADC
Paper in proceeding, 2018
We present design and evaluation of an asynchronous, alternating-comparator, 800MS/s SAR ADC. The comparators use continuous calibration to compensate for static input offset voltages. We use a combination of measurements and behavioural modelling to identify two possible causes of limited performance; leakage from the output drives onto the input signal, and dynamic offset voltage in the comparators.
SAR
ADC
Author
Victor Åberg
Chalmers, Computer Science and Engineering (Chalmers), Computer Engineering (Chalmers)
Christian Fager
Chalmers, Microtechnology and Nanoscience (MC2), Microwave Electronics
Lars Svensson
Chalmers, Computer Science and Engineering (Chalmers), Computer Engineering (Chalmers)
2018 IEEE Nordic Circuits and Systems Conference, NORCAS 2018: NORCHIP and International Symposium of System-on-Chip, SoC 2018 - Proceedings
8573500
978-1-5386-7656-1 (ISBN)
2018 IEEE Nordic Circuits and Systems Conference (NorCAS)
Tallinn, Estonia,
Tallinn, Estonia,
Areas of Advance
Information and Communication Technology
Subject Categories
Signal Processing
Other Electrical Engineering, Electronic Engineering, Information Engineering
DOI
10.1109/NORCHIP.2018.8573500