Lars Svensson
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Visar 58 publikationer
A 2x6b 8GS/s 17-24GHz I/Q RF-DAC based Transmitter in 22nm FDSOI CMOS
Hardware considerations for selection networks
Design Considerations and Evaluation of a High-Speed SAR ADC
Custom versus Cell-Based ASIC Design for Many-Channel Correlators
A Framework for a Relative Real-Time Tracking System Based on Ultra-Wideband Technology
ASIC Implementation of Time-Domain Digital Back Propagation for Coherent Receivers
Instruction level energy model for the Adapteva Epiphany multi-core processor
A 3-GHz Reconfigurable 2/3-Level 96/48-Channel Cross-Correlator for Synthetic Aperture Radiometry
Time-Domain Digital Back Propagation: Algorithm and Finite-Precision Implementation Aspects
Dynamic Equalizer Power Dissipation Optimization
Impact of Forward Error Correction on Energy Consumption of VCSEL-based Transmitters
A System-Level Mixed-Signal Design Course
A Novel Speculative Pseudo-Parallel \Delta\Sigma Modulator
Laptops in classroom interaction: Deconstructing the networked situation
On the Impact of Hardware Impairments on Massive MIMO
1.6 GHz Low-Power Cross-Correlator System Enabling Geostationary Earth Orbit Aperture Synthesis
3.6-GHz 0.2-mW/ch/GHz 65-nm Cross-Correlator for Synthetic Aperture Radiometry
On-chip Power Supply Noise and Its Implications on Timing
A Single-Chip 64 Input Low Power High Speed Cross-Correlator for Space Application
On-chip power supply noise and its implications on timing
Digital Cross-Correlators: Two Approaches
High-Performance 64-input Cross-Correlator
Towards Supply-Grid-Based Derating of Timing Margins
FlexCore: Utilizing Exposed Datapath Control for Efficient Computing
Supply Voltage Drop Study Considering On-Chip Self Inductance of a 32-bit Processor's Power Grid
Noise-Aware On-Chip Power Grid Considerations Using a Statistical Approach
Time-Domain Interconnect Characterisation Flow for Appropriate Model Segmentation
Noise Interaction Between Power Distribution Grids and Substrate
A New Master's Program in Integrated Electronic System Design
FlexCore: Utilizing Exposed Datapath Control for Efficient Computing
Overdrive Power-Gating Techniques for Total Power Minimization
Exposed Datapath for Efficient Computing
Toward a Systematic Sensitivity Analysis of On-Chip Power Grids Using Factor Analysis
Exposed Datapath for Efficient Computing
Interconnect Characterization Flow for Minimal-Segment Model Selection
Power-efficient, pulsed driving of capacitive loads to controllable voltage levels
Accounting for the Skin Effect during Repeater Insertion
On Skin Effect in On-Chip Interconnects
Frequency-Dependent Effects in RLC Interconnects
SYSTEM AND METHOD FOR IMPLEMENTING A SKEW-TOLERANT TRUE-SINGLE-PHASE-CLOCKING FLIP-FLOP
FlexSoC: Combining Flexibility and Efficiency in SoC Designs
A Mixed-Mode Delay-Locked Loop Architecture
Method for reducing EMI and IR-drop in digital synchronous circuits
Dual Threshold Voltage Circuits in the Presence of Resistive Interconnects
Using storage elements with multiple delay values to reduce current spikes in digital circuits
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