A Novel Speculative Pseudo-Parallel \Delta\Sigma Modulator
Paper i proceeding, 2015

We present a novel speculative pseudo-parallel \Delta\Sigma modulator structure, which almost halves the logic depth of the critical path in the pseudo-parallel Hatami structure. Following Hatami, our modulator calculates a block of n consecutive output bits in parallel, and then employs a parallelserial interface to output the bits at n times the modulator clock frequency. We circumvent the block-to-block dependence, which limits the clock speed of the Hatami structure, by speculatively calculating the outputs based on all possible output values of the previous block, and then selecting the correct one. We present cost and performance estimates for an initial implementation of the modulator, synthesized towards an FPGA and an ASIC technology.


Jesper Johansson

Chalmers, Data- och informationsteknik

Lars Svensson

Chalmers, Data- och informationsteknik, Datorteknik

32rd NORCHIP 2014

Article number 7004712- 7004712


Informations- och kommunikationsteknik



Annan elektroteknik och elektronik



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