On-chip power supply noise and its implications on timing
Paper i proceeding, 2010

We address two problems of assessing the influence of power- supply variations on timing analysis. We present a method to assign a supply-dependent hold margin; and we describe a method to accurately characterize logic gates for the sen- sitivity of delay on supply-voltage variations. We use a com- mercial microcontroller as a design example.

hold margins

supply-voltage variations

Författare

Lars Svensson

Chalmers, Data- och informationsteknik, Datorteknik

Johnny Pihl

Atmel Norway AS

Daniel A. Andersson

Atmel Norway AS

Per Larsson-Edefors

Chalmers, Data- och informationsteknik, Datorteknik

Proceedings of the ACM Great Lakes Symposium on VLSI, GLSVLSI

389-392

20th Great Lakes Symposium on VLSI, GLSVLSI 2010
Providence, USA,

Ämneskategorier

Annan maskinteknik

Transportteknik och logistik

Annan elektroteknik och elektronik

DOI

10.1145/1785481.1785571

Mer information

Senast uppdaterat

2020-08-05