On-chip power supply noise and its implications on timing
Paper in proceedings, 2010

We address two problems of assessing the influence of power- supply variations on timing analysis. We present a method to assign a supply-dependent hold margin; and we describe a method to accurately characterize logic gates for the sen- sitivity of delay on supply-voltage variations. We use a com- mercial microcontroller as a design example.

hold margins

supply-voltage variations

Author

Lars Svensson

Chalmers, Computer Science and Engineering (Chalmers), Computer Engineering (Chalmers)

Johnny Pihl

Atmel Norway AS

Daniel A. Andersson

Atmel Norway AS

Per Larsson-Edefors

Chalmers, Computer Science and Engineering (Chalmers), Computer Engineering (Chalmers)

Proceedings of the ACM Great Lakes Symposium on VLSI, GLSVLSI

389-392

20th Great Lakes Symposium on VLSI, GLSVLSI 2010
Providence, USA,

Subject Categories

Other Mechanical Engineering

Transport Systems and Logistics

Other Electrical Engineering, Electronic Engineering, Information Engineering

DOI

10.1145/1785481.1785571

More information

Latest update

8/5/2020 2