Method for reducing EMI and IR-drop in digital synchronous circuits

Patent, 2003

A method for designing a synchronous digital circuit that exploits clock skew so as to reduce EMI and IR-drop. The circuit has a plurality of storage elements connected to combinational logic blocks, each of the storage elements being driven by a clock signal distributed from a clock device; and the method involves substantially maximizing the clock skew in the circuit subject to one or more constraints on the design of the circuit.