Towards Supply-Grid-Based Derating of Timing Margins
Paper in proceedings, 2009

We investigate the influence of a realistic supply voltage network on the timing margins for a commercially-available 32-bit processor chip. Detailed models of the supply network and switching activity produce a spatial map of the supply voltage waveforms. We relate these waveforms to the expected excess logic delays, and estimate the required derating of the critical setup paths.

Author

Lars Svensson

Chalmers, Computer Science and Engineering (Chalmers), Computer Engineering (Chalmers)

Johnny Pihl

Atmel Norway AS

Daniel Andersson

Atmel Norway AS

Björn Nilsson

Chalmers, Computer Science and Engineering (Chalmers), Computer Engineering (Chalmers)

Per Larsson-Edefors

Chalmers, Computer Science and Engineering (Chalmers), Computer Engineering (Chalmers)

2009 IEEE Workshop on Signal Propagation on Interconnects, SPI '09; Strasbourg; France; 12 May 2009 through 15 May 2009

5089868

Subject Categories

Other Electrical Engineering, Electronic Engineering, Information Engineering

DOI

10.1109/SPI.2009.5089868

ISBN

978-142444489-2

More information

Created

10/7/2017