Manufacturable Nanometer Designs using Standard Cells with Regular Layout
Paper in proceedings, 2013

In addition to performance considerations, designing VLSI circuits at nanometer-scale process technology nodes demands considerations related to manufacturability and cost. Regular layout patterns are known to enhance resilience to random as well as certain types of systematic variations. In this contribution we assess the implications of this layout regularity using design automation for Critical Feature Analysis (CFA) and raw metrics, such as via count. Using the ISCAS’89 benchmark suite, for each benchmark circuit we compare place-and-route implementations that are based on semi-regular and ultra-regular cell layouts. While the CFA counter-intuitively suggests that implementations using ultra-regular layouts have lower Design for Manufacturability (DFM) scores than those using semi-regular layouts, we find that ultra-regular layouts yield implementations with an average of 22% fewer vias at the cost of a small wire length increase.

Author

KASYAB PARMESH SUBRAMANIYAN

Chalmers, Computer Science and Engineering (Chalmers), Computer Engineering (Chalmers)

Per Larsson-Edefors

Chalmers, Computer Science and Engineering (Chalmers), Computer Engineering (Chalmers)

Proceedings - International Symposium on Quality Electronic Design, ISQED

19483287 (ISSN) 19483295 (eISSN)

398-405 6523642

Areas of Advance

Information and Communication Technology

Subject Categories

Other Electrical Engineering, Electronic Engineering, Information Engineering

DOI

10.1109/ISQED.2013.6523642

ISBN

978-1-4673-4952-9

More information

Created

10/7/2017