Table-Based Total Power Consumption Estimation of Memory Arrays for Architects
Paper in proceeding, 2004
In this paper, we propose the White-box Table-based Total Power Consumption (WTTPC) estimation approach that offers both rapid and accurate architecture-level power estimation models for some processor components with regular structures, such as SRAM arrays, based on WTTPC-tables of
power values. A comparison of power estimates obtained from the proposed approach against circuit-level HSPICE power values for a 64-b conventional 6T-SRAM memory array implemented in a commercial 0.13-um CMOS technology process shows a 98% accuracy of the WTTPC approach.
Author
Minh Quang Do
Chalmers, Department of Computer Engineering, Embedded and Networked Processors
Per Larsson-Edefors
Chalmers, Department of Computer Engineering, Integrated Electronic Systems
Lars Bengtsson
Chalmers, Department of Computer Engineering, Embedded and Networked Processors
Lecture Notes in Computer Science (LNCS) , Springer Verlag
Vol. 3254 1 869-878
Subject Categories
Computer and Information Science
DOI
10.1007/978-3-540-30205-6_89