Synthesis and characterization of vertically aligned carbon nanofibers for nanoscale devices

Doctoral thesis, 2011

The synthesis of vertically aligned carbon nanofibers (VACNFs) by direct current plasma enhanced chemical vapor deposition (dc PECVD) has presented a unique opportunity to realize nanoscale three-dimensional devices at a reasonable cost. The determinism offered by the synthesis process in terms of control over the spatial and the geometrical properties of the resulting nanofibers provides a powerful tool to implement a wide range of applications from nanoelectromechanical systems to biological devices. However, the use of VACNFs as building blocks for nanoscale devices has not been a trivial task. The work presented in this thesis aims at incorporating the synthesis of VACNFs as an integral part of the nanofabrication process. The dc PECVD synthesis process is scrutinized by dividing it into three phases. The effect of growth parameters on each phase is investigated independently. Special attention is paid to the choice of materials involved in the synthesis process. Reactively sputtered TiN is chosen as the growth underlayer and a detailed discussion is given on its optimal deposition conditions. The material and process optimizations manifest themselves by a successful fabrication of individually addressable arrays of VACNFs with a sub-micrometer pitch between the adjacent nanofibers. The potential applications of such three-dimensional nanoscale arrays as well as a suitable measurement scheme are also discussed. As an important parameter for designing VACNF based devices, the bending stiffness of as-grown nanofibers is directly measured. It is shown that the assumption of a uniform internal structure is inadequate in describing nanofibers’ mechanical properties and that a dual phase model is needed in which different Young’s moduli are assigned to the inner graphitic core and the outer amorphous carbon shell. The potential of integrating the VACNF synthesis with CMOS technology is also assessed. The level of deterioration in the basic functionality of individual transistors on ASIC chips fabricated in standard 130 nm bulk CMOS technology are compared when the chips are subjected to three disparate CVD techniques with relatively low processing temperatures.