Understanding the Performance of Concurrent Data Structures on Graphics Processors
Paper in proceedings, 2012

In this paper we revisit the design of concurrent data structures -- specifically queues -- and examine their performance portability with regard to the move from conventional CPUs to graphics processors. We have looked at both lock-based and lock-free algorithms and have, for comparison, implemented and optimized the same algorithms on both graphics processors and multi-core CPUs. Particular interest has been paid to study the difference between the old Tesla and the new Fermi and Kepler architectures in this context. We provide a comprehensive evaluation and analysis of our implementations on all examined platforms. Our results indicate that the queues are in general performance portable, but that platform specific optimizations are possible to increase performance. The Fermi and Kepler GPUs, with optimized atomic operations, are observed to provide excellent scalability for both lock-based and lock-free queues.

cuda

gpgpu

queues

mpmc

spsc

data structures

performance portability

Author

Daniel Cederman

Chalmers, Computer Science and Engineering (Chalmers), Networks and Systems (Chalmers)

Bapi Chatterjee

Chalmers, Computer Science and Engineering (Chalmers), Networks and Systems (Chalmers)

Philippas Tsigas

Chalmers, Computer Science and Engineering (Chalmers), Networks and Systems (Chalmers)

Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)

03029743 (ISSN) 16113349 (eISSN)

Vol. 7484/2012 883-894

Areas of Advance

Information and Communication Technology

Subject Categories

Computer Science

DOI

10.1007/978-3-642-32820-6_87

ISBN

978-3-642-32819-0

More information

Created

10/6/2017