High-power SOI vertical DMOS transistors with lateral drain contacts: Process developments, characterization, and modeling
Journal article, 2004

Silicon-on-insulator (SOI) high-power vertical double-diffused MOS (VDMOS) transistors are demonstrated with a CMOS compatible fabrication process. A new backend trench formation process ensures a defect free device layer. Scanning electron microscope micrographs show that it is nearly free of defects. This has been achieved by moving the trench formation steps toward the end of the process. Our electrical measurements indicate that the transistors are fully functional. Electrothermal simulations show that unclamped inductive switching (UIS) test involves a substantial risk of turning the parasitic bipolar transistor (BJT) on. The UIS test is used to characterize the performance of power devices under unclamped inductive loading conditions. Extreme operating condition can be expected when all the energy stored in the inductor is released directly into device. Our measurements of the fabricated SOI VDMOSFET in the static region are in good agreement with the expected impact of the self-heating on the saturation behavior. The experiments at ambient temperature of 100°C show that the break down voltage decreases as the drain voltage increases. This indicates that a parasitic BJT has been turned on.

Author

Kuntjoro Pinardi

Chalmers, Microtechnology and Nanoscience (MC2), Solid State Electronics

Ulrich Heinle

Uppsala University

Stefan Bengtsson

Chalmers, Microtechnology and Nanoscience (MC2), Solid State Electronics

Jörgen Olsson

Uppsala University

J. P. Colinge

University of California

IEEE Transactions on Electron Devices

0018-9383 (ISSN)

Vol. 51 5 790-796

Subject Categories

Other Electrical Engineering, Electronic Engineering, Information Engineering

DOI

10.1109/TED.2004.825801

More information

Latest update

6/11/2018