Measurement, Modeling, and Characterization for Power-Aware Computing
Licentiate thesis, 2014

Society’s increasing dependence on information technology has resulted in the deployment of vast compute resources. The energy costs of operating these resources coupled with environmental concerns have made power-aware computing one of the primary challenges for the IT sector. Making energy-efficient computing a rule rather than an exception requires that researchers and system designers use the right set of techniques and tools. These involve measuring, modeling, and characterizing the energy consumption of computers at varying degrees of granularity. In this thesis, we present techniques to measure power consumption of computer systems at various levels. We compare them for accuracy and sensitivity and discuss their effectiveness. We test Intel’s hardware power model for estimation accuracy and show that it is fairly accurate for estimating energy consumption when sampled at the temporal granularity of more than tens of milliseconds. We present a methodology to estimate per-core processor power consumption using performance counter and temperature-based power modeling and validate it across multiple platforms. We show our model exhibits negligible computation overhead, and the median estimation errors ranges from 0.3% to 10.1% for applications from SPEC2006, SPEC-OMP and NAS benchmarks. We test the usefulness of the model in a meta-scheduler to enforce power constraint on a system. Finally, we perform a detailed performance and energy characterization of Intel’s Restricted Transactional Memory (RTM). We use TinySTM software transactional memory (STM) system to benchmark RTM’s performance against competing STM alternatives. We use microbenchmarks and STAMP benchmark suite to compare RTM versus STM performance and energy behavior. We quantify the RTM hardware limitations that affect its success rate. We show that RTM performs better than TinySTM when working-set fits inside the cache and that RTM is better at handling high contention workloads.

transactional memory

power management

energy characterization

power measurement

power estimation

power-aware scheduling

Room EA, EDIT Building
Opponent: Prof. Lieven Eeckhout, Ghent University, Belgium

Author

Bhavishya Goel

Chalmers, Computer Science and Engineering (Chalmers), Computer Engineering (Chalmers)

Techniques to Measure, Model, and Manage Power

Advances in Computers,; Vol. 87(2012)p. 7-54

Book chapter

Portable, scalable, per-core power estimation for intelligent resource management

International Green Computing Conference, 2010, Chicago, USA,; (2010)p. 135-146

Paper in proceedings

Subject Categories

Computer Engineering

Computer Systems

Technical report L - Department of Computer Science and Engineering, Chalmers University of Technology and Göteborg University: 111L

Publisher

Chalmers University of Technology

Room EA, EDIT Building

Opponent: Prof. Lieven Eeckhout, Ghent University, Belgium

More information

Latest update

11/11/2019