RSFQ Digital Signal Processor for Interference Cancellation
Paper in proceedings, 2004

RSFQ high performance Digital Signal processor capable to perform up to 13 13-bit fixed-point GMACS/s has been designed for use in Successive Interference Canceller in WCDMA wireless systems. The performance of the processor has been verified by numerical simulations and VHDL simulation using accurate modelling of the RSFQ gates. Components of the processor, 4x4 parallel multiplier 5x20 parallel dynamic memory and various control registers have been designed and experimentally tested.

RSFQ

Multiply-Accumulate unit

Successive Interference Canceller

Author

Irina Kataeva

Chalmers, Microtechnology and Nanoscience (MC2), Solid State Electronics

Hongxia Zhao

Chalmers, Signals and Systems, Communication and Antenna Systems, Communication Systems

Henrik Engseth

Chalmers, Microtechnology and Nanoscience (MC2), Solid State Electronics

Elena Tolkacheva

Chalmers, Microtechnology and Nanoscience (MC2), Solid State Electronics

Anna Kidiyarova-Shevchenko

Chalmers, Microtechnology and Nanoscience (MC2), Solid State Electronics

Applied superconductivity conference

Subject Categories

Physical Sciences

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Created

10/6/2017