High-performance clock-powered logic
Patent, 2006

High performance clock-powered logic runs at below supply levels and reduces the need for faster digital logic circuitry. In a preferred embodiment, a clocked buffer (101) is used to drive the signal line. The receiving end of the line is connected to a jam latch (123), preferably followed by an n-latch (125), followed by the digital logic (109), and followed by a second n-latch (127). The first n-latch is eliminated in an alternative embodiment, preferably one that uses complementary data signals.

Inventor

Lena Peterson

Chalmers, Computer Science and Engineering (Chalmers), Computer Engineering (Chalmers)

William C Athas

Weihua Mao

Nestor Tzartzanis

University of Southern California

7005893

10/031,672

Areas of Advance

Information and Communication Technology

Driving Forces

Sustainable development

Subject Categories

Electrical Engineering, Electronic Engineering, Information Engineering

Computer Systems

Other Electrical Engineering, Electronic Engineering, Information Engineering

More information

Latest update

10/15/2018