High-performance clock-powered logic
Patent, 2006

High performance clock-powered logic runs at below supply levels and reduces the need for faster digital logic circuitry. In a preferred embodiment, a clocked buffer (101) is used to drive the signal line. The receiving end of the line is connected to a jam latch (123), preferably followed by an n-latch (125), followed by the digital logic (109), and followed by a second n-latch (127). The first n-latch is eliminated in an alternative embodiment, preferably one that uses complementary data signals.

Uppfinnare

Lena Peterson

Chalmers, Data- och informationsteknik, Datorteknik

William C Athas

Organisation okänd

Weihua Mao

Organisation okänd

Nestor Tzartzanis

Organisation okänd

University of Southern California

7005893

10/031,672

Styrkeområden

Informations- och kommunikationsteknik

Drivkrafter

Hållbar utveckling

Ämneskategorier

Elektroteknik och elektronik

Datorsystem

Annan elektroteknik och elektronik

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Senast uppdaterat

2018-10-15