ECOSCALE: Reconfigurable computing and runtime system for future exascale systems
Paper in proceedings, 2016

In order to reach exascale performance, current HPC systems need to be improved. Simple hardware scaling is not a feasible solution due to the increasing utility costs and power consumption limitations. Apart from improvements in implementation technology, what is needed is to refine the HPC application development flow as well as the system architecture of future HPC systems. ECOSCALE tackles these challenges by proposing a scalable programming environment and architecture, aiming to substantially reduce energy consumption as well as data traffic and latency. ECOSCALE introduces a novel heterogeneous energy-efficient hierarchical architecture, as well as a hybrid many-core+OpenCL programming environment and runtime system. The ECOSCALE approach is hierarchical and is expected to scale well by partitioning the physical system into multiple independent Workers (i.e. compute nodes). Workers are interconnected in a tree-like fashion and define a contiguous global address space that can be viewed either as a set of partitions in a Partitioned Global Address Space (PGAS), or as a set of nodes hierarchically interconnected via an MPI protocol. To further increase energy efficiency, as well as to provide resilience, the Workers employ reconfigurable accelerators mapped into the virtual address space utilizing a dual stage System Memory Management Unit with coherent memory access. The architecture supports shared partitioned reconfigurable resources accessed by any Worker in a PGAS partition, as well as automated hardware synthesis of these resources from an OpenCL-based programming model.

Author

Iakovos Mavroidis

Telecommunication Systems Institute

Ioannis Papaefstathiou

Luciano Lavagno

Polytechnic University of Turin

Dimitrios S. Nikolopoulos

Queen's University Belfast

Dirk Koch

University of Manchester

John Goodacre

University of Manchester

Ioannis Sourdis

Chalmers, Computer Science and Engineering (Chalmers), Computer Engineering (Chalmers)

Vasileios Papaefstathiou

Chalmers, Computer Science and Engineering (Chalmers), Computer Engineering (Chalmers)

Marcello Coppola

STMicroelectronics SA, France

Manuel Palomino

Acciona S.A.

19th Design, Automation and Test in Europe Conference and Exhibition, DATE 2016, Dresden, Germany, 14-18 March 2016

1530-1591 (ISSN)

696-701

Subject Categories

Computer Science

ISBN

978-3-9815-3706-2

More information

Latest update

9/6/2018 2