Vasileios Papaefstathiou
Showing 23 publications
eProcessor: European, Extendable, Energy-Efficient, Extreme-Scale, Extensible, Processor Ecosystem
HighwayNoC: Approaching Ideal NoC Performance With Dual Data Rate Routers
UNILOGIC: A Novel Architecture for Highly Parallel Reconfigurable Systems
Hybrid2: Combining Caching and Migration in Hybrid Memory Systems
LLC-guided data migration in hybrid memory systems
Decoupled fused cache: Fusing a decoupled LLC with a DRAM cache
FusionCache: Using LLC tags for DRAM cache
Global dead-block management for task-parallel programs
FreewayNoC: A DDR NoC with Pipeline Bypassing
ProFess: A Probabilistic Hybrid Main Memory Management Framework for High Performance and Fairness
DDRNoC: Dual Data-Rate Network-on-Chip
Runtime-Assisted Global Cache Management for Task-based Parallel Programs
SLOOP: QoS-Supervised Loop Execution to Reduce Energy on Heterogeneous Architectures
Odd-ECC: On-demand DRAM error correcting codes
RADAR: Runtime-assisted dead region management for last-level caches
Adaptive row addressing for cost-efficient parallel memory protocols in large-capacity memories
RADAR: Run-time assisted Dead-Region Management for Last-Level Caches
ProF: Probabilistic Hybrid Main Memory Management for High Performance and Fairness
ECOSCALE: Reconfigurable computing and runtime system for future exascale systems
A Case for Runtime-Assisted Global Cache Management
Design trade-offs in energy efficient NoC architectures
RADAR: Runtime-Assisted Dead Region Management for Last-Level Caches
A systematic evaluation of emerging mesh-like CMP NoCs
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Showing 1 research projects
Energy-efficient Heterogeneous COmputing at exaSCALE (ECOSCALE)