Vasileios Papaefstathiou

Showing 14 publications

2018

DDRNoC: Dual Data-Rate Network-on-Chip

Ahsen Ejaz, Vasileios Papaefstathiou, Ioannis Sourdis
Transactions on Architecture and Code Optimization. Vol. 15 (2)
Journal article
2018

Global dead-block management for task-parallel programs

Madhavan Manivannan, Miquel Pericas, Vasileios Papaefstathiou et al
Transactions on Architecture and Code Optimization. Vol. 15 (3)
Journal article
2017

Runtime-Assisted Global Cache Management for Task-based Parallel Programs

Madhavan Manivannan, Miquel Pericas, Vasileios Papaefstathiou et al
IEEE Computer Architecture Letters. Vol. 16 (2), p. 145-148
Journal article
2017

Odd-ECC: On-demand DRAM error correcting codes

Alirad Malek, E. Vasilakis, Vasileios Papaefstathiou et al
ACM International Conference Proceeding Series. Vol. Part F131197, p. 96-101
Paper in proceedings
2017

SLOOP: QoS-Supervised Loop Execution to Reduce Energy on Heterogeneous Architectures

Muhammad Waqar Azhar, Per Stenström, Vasileios Papaefstathiou
ACM Transactions on Architecture and Code Optimization. Vol. 14 (4), p. Article No. 41-
Journal article
2016

A Case for Runtime-Assisted Global Cache Management

Madhavan Manivannan, Miquel Pericas, Vasileios Papaefstathiou et al
Report
2016

RADAR: Run-time assisted Dead-Region Management for Last-Level Caches

Madhavan Manivannan, Miquel Pericas, Vasileios Papaefstathiou et al
IEEE International Symposium on High Performance Computer Architecture, p. 11-
Paper in proceedings
2016

RADAR: Runtime-assisted dead region management for last-level caches

Madhavan Manivannan, Vasileios Papaefstathiou, Miquel Pericas et al
22nd IEEE International Symposium on High Performance Computer Architecture, HPCA 2016, Barcelona, Spain, 12-16 March 2016, p. 644-656
Paper in proceedings
2016

ECOSCALE: Reconfigurable computing and runtime system for future exascale systems

Iakovos Mavroidis, Ioannis Papaefstathiou, Luciano Lavagno et al
19th Design, Automation and Test in Europe Conference and Exhibition, DATE 2016, Dresden, Germany, 14-18 March 2016, p. 696-701
Paper in proceedings
2016

Adaptive row addressing for cost-efficient parallel memory protocols in large-capacity memories

Dmitry Knyaginin, Vasileios Papaefstathiou, Per Stenström
MEMSYS 2016: International Symposium on Memory Systems. Vol. 03-06-October-2016, p. 121-132
Paper in proceedings
2016

ProF: Probabilistic Hybrid Main Memory Management for High Performance and Fairness

Dmitry Knyaginin, Per Stenström, Vasileios Papaefstathiou
Report
2015

A systematic evaluation of emerging mesh-like CMP NoCs

A. Psathakis, Vasileios Papaefstathiou, N. Chrysos et al
ANCS 2015 - 11th 2015 ACM/IEEE Symposium on Architectures for Networking and Communications Systems, p. 159-170
Paper in proceedings
2015

RADAR: Runtime-Assisted Dead Region Management for Last-Level Caches

Madhavan Manivannan, Vasileios Papaefstathiou, Miquel Pericas et al
Report
2014

Design trade-offs in energy efficient NoC architectures

A. Psathakis, Vasileios Papaefstathiou, M. Katevenis et al
8th IEEE/ACM International Symposium on Networks-on-Chip, NoCS 2014; Ferrara; Italy; 17 September 2014 through 19 September 2014, p. 186-187
Paper in proceedings

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