Energy-efficient Heterogeneous COmputing at exaSCALE (ECOSCALE)
Forskningsprojekt , 2015 – 2018

In order to reach exascale performance current HPC servers need to be improved. Simple scaling is not a feasible solution due to the increasing utility costs and power consumption limitations. Apart from improvements in implementation technology, what is needed is to refine the HPC application development as well as the architecture of the future HPC systems. ECOSCALE tackles this challenge by proposing a scalable programming environment and hardware architecture tailored to the characteristics and trends of current and future HPC applications, reducing significantly the data traffic as well as the energy consumption and delays. We first propose a novel heterogeneous energy-efficient hierarchical architecture and a hybrid MPI+OpenCL programming environment and runtime system. The proposed architecture, programming model and runtime system follows a hierarchical approach where the system is partitioned into multiple autonomous Workers (i.e. compute nodes). Workers are interconnected in a tree-like structure in order to form larger Partitioned Global Address Space (PGAS) partitions, which are further hierarchically interconnected via an MPI protocol. Secondly, to further increase the energy efficiency of the system as well as its resilience, the Workers will employ reconfigurable accelerators that can perform coherent memory accesses in the virtual address space utilizing an IOMMU. The ECOSCALE architecture will support shared partitioned reconfigurable resources accessed by any Worker in a PGAS partition, and, more importantly, automated hardware synthesis of these resources from an OpenCL-based programming model. We follow a co-design approach that spans a scalable HPC hardware platform, a middleware layer, a programming and a runtime environment as well as a high-level design environment for mapping applications onto the system. A proof of concept prototype and a simulator will be built in order to run two real-world HPC applications and several benchmarks.

Deltagare

Ioannis Sourdis (kontakt)

Biträdande professor vid Chalmers, Data- och informationsteknik, Datorteknik

Vasileios Papaefstathiou

Forskare vid Chalmers, Data- och informationsteknik, Datorteknik

Samarbetspartners

Acciona Infraestructuras

Alcobendas-Madrid, Spain

Politecnico di Torino

Torino, Italy

Queen's University Belfast

Belfast, United Kingdom

STMicroelectronics, Grenoble 2 Sas

Grenoble, France

Synelixis Solutions

Chalkida, Greece

Telecommunication Systems Institute

Chania, Greece

University of Manchester

Manchester, United Kingdom

Finansiering

Europeiska kommissionen (Horisont 2020)

Finansierar Chalmers deltagande under 2015–2018

Relaterade styrkeområden och infrastruktur

Informations- och kommunikationsteknik

Styrkeområden

Hållbar utveckling

Drivkrafter

Publikationer

2018

DDRNoC: Dual Data-Rate Network-on-Chip

Licentiatavhandling

Mer information

Projektets webbplats

http://www.ecoscale.eu/

Senast uppdaterat

2016-01-28