Vasileios Papaefstathiou

Visar 23 publikationer

2023

eProcessor: European, Extendable, Energy-Efficient, Extreme-Scale, Extensible, Processor Ecosystem

Lluc Alvarez, Abraham Ruiz, Arnau Bigas-Soldevilla et al
Proceedings of the 20th ACM International Conference on Computing Frontiers 2023, CF 2023, p. 309-314
Paper i proceeding
2021

HighwayNoC: Approaching Ideal NoC Performance With Dual Data Rate Routers

Ahsen Ejaz, Vasileios Papaefstathiou, Ioannis Sourdis
IEEE/ACM Transactions on Networking. Vol. 29 (1), p. 318-331
Artikel i vetenskaplig tidskrift
2020

UNILOGIC: A Novel Architecture for Highly Parallel Reconfigurable Systems

Aggelos D. Ioannou, Konstantinos Georgopoulos, Pavlos Malakonakis et al
ACM Transactions on Reconfigurable Technology and Systems. Vol. 13 (4)
Artikel i vetenskaplig tidskrift
2020

Hybrid2: Combining Caching and Migration in Hybrid Memory Systems

Evangelos Vasilakis, Vasileios Papaefstathiou, Pedro Petersen Moura Trancoso et al
Proceedings - International Symposium on High-Performance Computer Architecture, p. 649-662
Paper i proceeding
2019

LLC-guided data migration in hybrid memory systems

Evangelos Vasilakis, Vasileios Papaefstathiou, Pedro Petersen Moura Trancoso et al
Proceedings - 2019 IEEE 33rd International Parallel and Distributed Processing Symposium, IPDPS 2019, p. 932-942
Paper i proceeding
2019

Decoupled fused cache: Fusing a decoupled LLC with a DRAM cache

Evangelos Vasilakis, Vasileios Papaefstathiou, Pedro Petersen Moura Trancoso et al
Transactions on Architecture and Code Optimization. Vol. 15 (4)
Artikel i vetenskaplig tidskrift
2018

FusionCache: Using LLC tags for DRAM cache

Evangelos Vasilakis, Vasileios Papaefstathiou, Pedro Petersen Moura Trancoso et al
Proceedings of the 2018 Design, Automation and Test in Europe Conference and Exhibition, DATE 2018. Vol. 2018-January, p. 593-596
Paper i proceeding
2018

Global dead-block management for task-parallel programs

Madhavan Manivannan, Miquel Pericas, Vasileios Papaefstathiou et al
Transactions on Architecture and Code Optimization. Vol. 15 (3)
Artikel i vetenskaplig tidskrift
2018

FreewayNoC: A DDR NoC with Pipeline Bypassing

Ahsen Ejaz, Vasileios Papaefstathiou, Ioannis Sourdis
2018 12th IEEE/ACM International Symposium on Networks-on-Chip, NOCS 2018
Paper i proceeding
2018

ProFess: A Probabilistic Hybrid Main Memory Management Framework for High Performance and Fairness

Dmitry Knyaginin, Vasileios Papaefstathiou, Per Stenström
Proceedings - International Symposium on High-Performance Computer Architecture. Vol. 2018-February, p. 143-155
Paper i proceeding
2018

DDRNoC: Dual Data-Rate Network-on-Chip

Ahsen Ejaz, Vasileios Papaefstathiou, Ioannis Sourdis
Transactions on Architecture and Code Optimization. Vol. 15 (2)
Artikel i vetenskaplig tidskrift
2017

Runtime-Assisted Global Cache Management for Task-based Parallel Programs

Madhavan Manivannan, Miquel Pericas, Vasileios Papaefstathiou et al
IEEE Computer Architecture Letters. Vol. 16 (2), p. 145-148
Artikel i vetenskaplig tidskrift
2017

SLOOP: QoS-Supervised Loop Execution to Reduce Energy on Heterogeneous Architectures

Muhammad Waqar Azhar, Per Stenström, Vasileios Papaefstathiou
Transactions on Architecture and Code Optimization. Vol. 14 (4), p. Article No. 41-
Artikel i vetenskaplig tidskrift
2017

Odd-ECC: On-demand DRAM error correcting codes

Alirad Malek, Evangelos Vasilakis, Vasileios Papaefstathiou et al
ACM International Conference Proceeding Series. Vol. Part F131197, p. 96-101
Paper i proceeding
2016

RADAR: Runtime-assisted dead region management for last-level caches

Madhavan Manivannan, Vasileios Papaefstathiou, Miquel Pericas et al
Proceedings - International Symposium on High-Performance Computer Architecture. Vol. 2016-April, p. 644-656
Paper i proceeding
2016

Adaptive row addressing for cost-efficient parallel memory protocols in large-capacity memories

Dmitry Knyaginin, Vasileios Papaefstathiou, Per Stenström
MEMSYS 2016: International Symposium on Memory Systems. Vol. 03-06-October-2016, p. 121-132
Paper i proceeding
2016

RADAR: Run-time assisted Dead-Region Management for Last-Level Caches

Madhavan Manivannan, Miquel Pericas, Vasileios Papaefstathiou et al
IEEE International Symposium on High Performance Computer Architecture, p. 11-
Paper i proceeding
2016

ProF: Probabilistic Hybrid Main Memory Management for High Performance and Fairness

Dmitry Knyaginin, Per Stenström, Vasileios Papaefstathiou
Rapport
2016

ECOSCALE: Reconfigurable computing and runtime system for future exascale systems

Iakovos Mavroidis, Ioannis Papaefstathiou, Luciano Lavagno et al
19th Design, Automation and Test in Europe Conference and Exhibition, DATE 2016, Dresden, Germany, 14-18 March 2016, p. 696-701
Paper i proceeding
2016

A Case for Runtime-Assisted Global Cache Management

Madhavan Manivannan, Miquel Pericas, Vasileios Papaefstathiou et al
Rapport
2015

Design trade-offs in energy efficient NoC architectures

A. Psathakis, Vasileios Papaefstathiou, M. Katevenis et al
8th IEEE/ACM International Symposium on Networks-on-Chip, NoCS 2014; Ferrara; Italy; 17 September 2014 through 19 September 2014, p. 186-187
Paper i proceeding
2015

RADAR: Runtime-Assisted Dead Region Management for Last-Level Caches

Madhavan Manivannan, Vasileios Papaefstathiou, Miquel Pericas et al
Rapport
2015

A systematic evaluation of emerging mesh-like CMP NoCs

A. Psathakis, Vasileios Papaefstathiou, N. Chrysos et al
ANCS 2015 - 11th 2015 ACM/IEEE Symposium on Architectures for Networking and Communications Systems, p. 159-170
Paper i proceeding

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Visar 1 forskningsprojekt

2015–2018

Energy-efficient Heterogeneous COmputing at exaSCALE (ECOSCALE)

Vasileios Papaefstathiou Datorteknik
Ioannis Sourdis Datorteknik
Europeiska kommissionen (EU)

12 publikationer finns
Det kan finnas fler projekt där Vasileios Papaefstathiou medverkar, men du måste vara inloggad som anställd på Chalmers för att kunna se dem.