DDRNoC: Dual Data-Rate Network-on-Chip
Implementation of the DDRNoC and FreewayNoC architectures require redesign of the switch allocation (SA) mechanism to resolve contention among competing its by granting up to two its access to each switch input and output port per clock cycle. It further requires separate paths for the propagation of lookahead control signals. FreewayNoC also requires implementation of multiple checks to guarantee con ict-free bypassing of the SA stage.
Physical implementation results using 28nm process technology show that DDRNoC and FreewayNoC have 5% and 15% area overhead, respectively, compared to a simple 3-stage network with VCs. Performance evaluation shows that for a 16X16 mesh network, FreewayNoC supports 25% higher throughput compared to current state-of-the-art NoC, ShortPath. Moreover, FreewayNoC achieves a zero-load latency which scales better than ShortPath and equally well with an ideal network that has no control overheads. For application driven traffic, FreewayNoC reduces average packet latency by 18% compared to ShortPath. Alternatively, low voltage implementation of the DDRNoC and FreewayNoC can be used to conserve power and improve energy efficiency at the cost of higher packet latency.
Chalmers, Data- och informationsteknik, Datorteknik
Green Computing Node for European micro-servers (EUROSERVER)
Europeiska kommissionen (FP7), 2013-09-01 -- 2016-08-31.
Energy-efficient Heterogeneous COmputing at exaSCALE (ECOSCALE)
Europeiska kommissionen (Horisont 2020), 2015-10-01 -- 2018-12-31.
Informations- och kommunikationsteknik
Technical report L - School of Computer Science and Engineering, Chalmers University of Technology: 180
Chalmers tekniska högskola
ES52, Rännvägen 6
Opponent: Assistant Professor Giorgos Dimitrakopoulos, Democritus University of Thrace, Greece