Ioannis Sourdis
Visar 67 publikationer
A Parallel Hash Table for Streaming Applications
BZSim: Fast, Large-Scale Microarchitectural Simulation with Detailed Interconnect Modeling
Stream Aggregation with Compressed Sliding Windows
eProcessor: European, Extendable, Energy-Efficient, Extreme-Scale, Extensible, Processor Ecosystem
FastTrackNoC: A NoC with FastTrack Router Datapaths
FlatPack: Flexible Compaction of Compressed Memory
L2C: Combining Lossy and Lossless Compression on Memory and I/O
Reliability Analysis of Compressed CNNs
Introduction to the Special Section on FPL 2019
Streamzip: Compressed Sliding-Windows for Stream Aggregation
HighwayNoC: Approaching Ideal NoC Performance With Dual Data Rate Routers
A Specialized Memory Hierarchy for Stream Aggregation
MemSZ: Squeezing Memory Traffic with Lossy Compression
Hybrid2: Combining Caching and Migration in Hybrid Memory Systems
Mapping Multiple LSTM models on FPGAs
LLC-guided data migration in hybrid memory systems
Energy-efficient Runtime Management of Heterogeneous Multicores using Online Projection
AVR: Reducing Memory Traffic with Approximate Value Reconstruction
Time-SWAD: A dataflow engine for time-based single window stream aggregation
Decoupled fused cache: Fusing a decoupled LLC with a DRAM cache
FusionCache: Using LLC tags for DRAM cache
COSSIM: An open-source integrated solution to address the simulator gap for systems of systems
FreewayNoC: A DDR NoC with Pipeline Bypassing
Attacks on Heartbeat-Based Security Using Remote Photoplethysmography
DDRNoC: Dual Data-Rate Network-on-Chip
Single Window Stream Aggregation using Reconfigurable Hardware
Modeling Energy-Performance Tradeoffs in ARM big. LITTLE Architectures
Towards real-time whisker tracking in rodents for studying sensorimotor disorders
Enhancing heart-beat-based security for mHealth applications
SWAS: Stealing Work Using Approximate System-Load Information
DDRNoC: Dual Data-Rate Network-on-Chip
Odd-ECC: On-demand DRAM error correcting codes
BrainFrame: a node-level heterogeneous accelerator platform for neuron simulations
Secure key-exchange protocol for implants using heartbeats
RQNoC: A resilient quality-of-service network-on-chip with service redirection
Performance Analysis of Accelerated Biophysically-Meaningful Neuron Simulations
Runtime Management of Adaptive MPSoCs for Graceful Degradation
ECOSCALE: Reconfigurable computing and runtime system for future exascale systems
Resilient chip multiprocessors with mixed-grained reconfigurability
Secure hardware-software architectures for robust computing systems
Reducing the performance overhead of resilient CMPs with substitutable resources
Increasing the Trustworthiness of Embedded Applications
On using a von neumann extractor in heart-beat-based security
A Probabilistic Analysis of Resilient Reconfigurable Designs
Peak misdetection in heart-beat-based security: Characterization and tolerance
DeSyRe: On-demand adaptive and reconfigurable fault-tolerant SoCs
A dependable coarse-grain reconfigurable multicore array
A runtime manager for gracefully degrading SoCs
FPGA-based biophysically-meaningful modeling of olivocerebellar neurons
The DeSyRe runtime support for fault-tolerant embedded MPSoCs
Design and analysis of binary tree static random access memory for low power embedded systems
Real-time olivary neuron simulations on dataflow computing machines
Adaptive entity-identifier generation for IMD emergency access
Guest editorial: Workshop on Reconfigurable Computing
Heuristic Search for Adaptive, Defect-Tolerant Multiprocessor Arrays
DeSyRe: On-demand system reliability
Software modification aided transient error tolerance for embedded systems
on-Demand System Reliability: The DeSyRe project
A System Architecture, Processor, and Communication Protocol for Secure Implants
The DeSyRe Project: On-Demand System Reliability
Reconfigurable Acceleration and Dynamic Partial Self-Reconfiguration in General Purpose Computing
Hardware OS Communication Service and Dynamic Memory Management for RSoCs
Communication Service for hardware tasks executed on dynamic and partial reconfigurable resource
Longest prefix match and updates in range tries
HiPEAC: Upcoming Challenges in Reconfigurable Computing
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Visar 14 forskningsprojekt
EUMMSS: Efficient Uncore Mechanisms for Multicore Space Systems
Pilot using Independent Local & Open Technologies (The European PILOT)
CSSTII Certifierbara System-på-Kisel för säkerhetskritiska tillämpningar Inom Industrin
Principer för beräknande minnesenheter (PRIDE)
ScalaNetS: Skalbara nätverks- och dataströmsberäkningar
Energy-efficient Heterogeneous COmputing at exaSCALE (ECOSCALE)
ACE: Approximativa algoritmer och datorsystem
Secure Hardware-Software Architectures for Robust Computing Systems (SHARCS)
A Novel, Comprehensible, Ultra-Fast, Security-Aware CPS Simulator (COSSIM)
Green Computing Node for European micro-servers (EUROSERVER)
on-Demand System Reliability (DeSyRe)