Heuristic Search for Adaptive, Defect-Tolerant Multiprocessor Arrays
Artikel i vetenskaplig tidskrift, 2013

In this article, new heuristic-search methods and algorithms are presented for enabling highly efficient and adaptive, defect-tolerant multiprocessor arrays. We consider systems where a homogeneous multiprocessor array lies on top of reconfigurable interconnects which allow the pipeline stages of the processors to be connected in all possible configurations. Considering the multiprocessor array partitioned in substitutable units at the granularity of pipeline stages, we employ a variety of heuristic-search methods and algorithms to isolate and replace defective units. The proposed heuristics are designed for off-line execution and aim at minimizing the performance overhead necessarily introduced to the array by the interconnects' latency. An empirical evaluation of the designed algorithms is then carried out, in order to assess the targeted problem and the efficacy of our approach. Our findings indicate this to be a NP-complete computational problem, however, our heuristic-search methods can achieve, for the problem sizes we exhaustively searched, 100% accuracy in finding the optimal solution among 10(19) possible candidates within 2.5 seconds. Alternatively, they can provide near-optimal solutions at an accuracy which consistently exceeds 70% (compared to the optimal solution) in only 10(-4) seconds.


Heuristic methods


adaptable architectures




V. Vasilikos

TU Delft

G. Smaragdos

TU Delft

C. Strydis

Erasmus Universiteit Rotterdam

Ioannis Sourdis

Chalmers, Data- och informationsteknik, Datorteknik

Transactions on Embedded Computing Systems

1539-9087 (ISSN) 15583465 (eISSN)

Vol. 12 SUPPL1 44


Informations- och kommunikationsteknik


Data- och informationsvetenskap



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